openpower.mdwn

   1 # Evaluation
   2
   3 * FP32 is converted to FP64. Requires SV to be active.
   4 * FP16 needed
   5 * FCVT between 16/32/64 needed
   6 * c++11 atomics not very efficient
   7 * no 16/48/64 opcodes, needs a shuffle of opcodes
   8 * needs escape sequencing (ISAMUX/NS)
   9
  10 # atomics
  11
  12 Single instruction on RV, and x86, but multiple on Power. Needs investigation, particularly as to why cache flush exists.
  13
  14 # FP16
  15
  16 Doesn't exist in Power, need to work out suitable opcodes, basically means duplicating the entire range of FP32/64 ops, symmetrically.
  17
  18 Usually done with a fmt field, 2 bit, last one is FP128
  19
  20 # Escape Sequencing
  21
  22 Absolutely critical, also to have official endorsement from OpenPower Foundation.
  23
  24 # Compressed, 48, 64, VBLOCK
  25
  26 Under Esc Seq, move mulli, twi, tdi out of major OP000 then use the entire row, 2 bits instead of 3.
  27
  28 * OP 000-000 and 000-001 for 16 bit compressed, 11 bit instructions
  29 * OP 000-010 and 000-011 for 48 bit. 11 bits for SVP P48
  30 * OP 000-100 and 000-201 for 64 bit. 11 bits for SVP P64
  31 * OP 000-110 and 000-111 for VBLOCK. 11 bits available.
  32
  33 # Compressed 16
  34
  35 Only 11 bits. Idea: have "pages" where one instruction selects the page number. It also specifies for how long that page is activated (terminated on a branch)
  36
  37 The length to be a maximum of 4 bits, where 0b1111 indicates "permanently active".
  38
  39 Perhaps split OP000-000 and OP000-001 so that 2 pages can be active.
  40
  41 Store activation length in a CSR.