openpower.mdwn

   1 # Evaluation
   2
   3 EULA released! looks good.
   4
   5 Links
   6
   7 * OpenPower HDL Mailing list <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-hdl-cores>
   8 * [[openpower/isatables]]
   9 * [[openpower/gem5]]
  10 * [[3d_gpu/architecture/decoder]]
  11 * <https://forums.raptorcs.com/>
  12 * <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-community-dev>
  13 * <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo>
  14 * <http://bugs.libre-riscv.org/show_bug.cgi?id=179>
  15 * <https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0>
  16 * <https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b>
  17
  18 Summary
  19
  20 * FP32 is converted to FP64. Requires SimpleV to be active.
  21 * FP16 needed
  22 * transcendental FP opcodes needed (sin, cos, atan2, root, log1p)
  23 * FCVT between 16/32/64 needed
  24 * c++11 atomics not very efficient
  25 * no 16/48/64 opcodes, needs a shuffle of opcodes.  TODO investigate Power VLE
  26 * needs escape sequencing (ISAMUX/NS)
  27
  28 # What we are *NOT* doing:
  29
  30 * A processor that is fundamentally incompatible (noncompliant) with Power.
  31  (**escape-sequencing requires and guarantees compatibility**).
  32 * Opcode 4 Signal Processing (SPE)
  33 * Opcode 4 Vectors or Opcode 60 VSX
  34 * Avoidable legacy opcodes
  35
  36 # SimpleV
  37
  38 see [[simple_v_extension]] - will fit into 48/64/VBLOCK, see below.
  39 SimpleV: a "hardware for-loop" which involves type-casting (both) the
  40 register files to "a sequence of elements".  The **one** instruction
  41 (an unmodified **scalar** instruction) is interpreted as a *hardware
  42 for-loop* that issues **multiple** internal instructions with
  43 sequentially-incrementing register numbers.
  44
  45 Thus it is completely unnecessary to add any vector opcodes - at all -
  46 saving hugely on both hardware and compiler development time when
  47 the concept is dropped on top of a pre-existing ISA.
  48
  49 ## Condition Registers
  50
  51 Branch Facility (Section 2.3.1 V2.07B and V3.0B) has 4-bit registers: CR0 and CR1.  When SimpleV is active, it may be better to set CR6 (the Vector CR field) instead.
  52
  53 ## Carry
  54
  55 SimpleV extends (wraps) *scalar* opcodes with a hardware-level for-loop. Therefore, each scalar operation with a carry-in and carry-out will **require its own carry in and out bit**. Therefore, an extra SPR will be required which allows context switches to save this full set of carry bits.
  56
  57 # Integer Overflow / Saturate
  58
  59 Typically used on vector operations (audio DSP), it makes no sense to have separate opcodes (Opcode 4 SPE).  To be done instead as CSRs / vector-flags on *standard* arithmetic operations.
  60
  61 # atomics
  62
  63 Single instruction on RV, and x86, but multiple on Power. Needs investigation, particularly as to why cache flush exists.
  64
  65 https://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
  66
  67 Hot loops contain significant instruction count, really need new c++11 atomics.  To be proposed as new extension because other OpenPower members will need them too
  68
  69 # FP16
  70
  71 Doesn't exist in Power, need to work out suitable opcodes, basically means duplicating the entire range of FP32/64 ops, symmetrically.
  72
  73 Usually done with a fmt field, 2 bit, last one is FP128
  74
  75 idea: rather than add dozens of new opcodes, add "repurposer" instructions that remap FP32 to 16/32/64/128 and FP64 likewise.  can also be done as C instruction, only needs 4 bits to specify.
  76
  77 # Escape Sequencing
  78
  79 aka "ISAMUX/NS".  Absolutely critical, also to have official endorsement
  80 from OpenPower Foundation.
  81
  82 This will allow extending ISA (see ISAMUX/NS) in a clean fashion
  83 (including for and by OpenPower Foundation)
  84
  85 ## Branches in namespaces
  86
  87 Branches are fine as it is up to the compiler to decide whether to let the
  88 ISAMUX/NS/escape-sequence countdown run out.
  89
  90 This is all a software / compiler / ABI issue.
  91
  92 ## Function calls in namespaces
  93
  94 Storing and restoring the state of the page/subpage CSR should be done by the caller. Or, again, let the countdowns run out.
  95
  96 If certain alternative configs are expected, they are part of the function ABI which must be spec'd.
  97
  98 All of this is a software issue (compiler / ABI).
  99
 100 # Compressed, 48, 64, VBLOCK
 101
 102 TODO investigate Power VLE (Freescale doc Ref 314-68105)
 103
 104 Under Esc Seq, move mulli, twi, tdi out of major OP000 then use the
 105 entire row, 2 bits instead of 3.  greatly simplifies decoder.
 106
 107 * OP 000-000 and 000-001 for 16 bit compressed, 11 bit instructions
 108 * OP 000-010 and 000-011 for 48 bit. 11 bits for SVP P48
 109 * OP 000-100 and 000-201 for 64 bit. 11 bits for SVP P64
 110 * OP 000-110 and 000-111 for VBLOCK. 11 bits available.
 111
 112 # Compressed 16
 113
 114 Further "escape-sequencing".
 115
 116 Only 11 bits available. Idea: have "pages" where one instruction selects
 117 the page number. It also specifies for how long that page is activated
 118 (terminated on a branch)
 119
 120 The length to be a maximum of 4 bits, where 0b1111 indicates "permanently active".
 121
 122 Perhaps split OP000-000 and OP000-001 so that 2 pages can be active.
 123
 124 Store activation length in a CSR.
 125
 126 2nd idea: 11 bits can be used for extremely common operations, then length-encoding page selection for further ops, using the full 16 bit range and an entirely new encoding scheme. 1 bit specifies which of 2 pages was selected?
 127
 128 3rd idea: "stack" mechanism. Allow subpages like a stack, to page in new pages.
 129
 130 3 bits for subpage number. 4 bits for length, gives 7 bits. 4x7 is 28, then 3 bits can be used to specify "stack depth".
 131
 132 Requirements are to have one instruction in each subpage which resets all the way back to PowerISA default. The other is a "back up stack by 1".
 133
 134 # RISCV userspace
 135
 136 Dual ISA, RV userspace only. Requires PowerISA to be able to context-switch RV registers and CSRs.
 137
 138 the exception entry point:
 139 https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/exceptions-64s.S?h=v5.4-rc5#n409
 140
 141 the rest of the context switch code is in a different file:
 142 https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/entry_64.S?h=v5.4-rc5#n589