openpower.mdwn

   1 # Evaluation
   2
   3 EULA released! looks good.
   4
   5 Links
   6
   7 * OpenPower HDL Mailing list <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-hdl-cores>
   8 * [[openpower/isatables]]
   9 * [[3d_gpu/architecture/decoder]]
  10 * <https://forums.raptorcs.com/>
  11 * <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo/openpower-community-dev>
  12 * <http://lists.mailinglist.openpowerfoundation.org/mailman/listinfo>
  13 * <http://bugs.libre-riscv.org/show_bug.cgi?id=179>
  14 * <https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0>
  15 * <https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b>
  16
  17 Summary
  18
  19 * FP32 is converted to FP64. Requires SimpleV to be active.
  20 * FP16 needed
  21 * transcendental FP opcodes needed (sin, cos, atan2, root, log1p)
  22 * FCVT between 16/32/64 needed
  23 * c++11 atomics not very efficient
  24 * no 16/48/64 opcodes, needs a shuffle of opcodes.  TODO investigate Power VLE
  25 * needs escape sequencing (ISAMUX/NS)
  26
  27 # What we are *NOT* doing:
  28
  29 * A processor that is fundamentally incompatible (noncompliant) with Power.
  30  (**escape-sequencing requires and guarantees compatibility**).
  31 * Opcode 4 Signal Processing (SPE)
  32 * Opcode 4 Vectors or Opcode 60 VSX
  33 * Avoidable legacy opcodes
  34
  35 # SimpleV
  36
  37 see [[simple_v_extension]] - will fit into 48/64/VBLOCK, see below.
  38 SimpleV: a "hardware for-loop" which involves type-casting (both) the
  39 register files to "a sequence of elements".  The **one** instruction
  40 (an unmodified **scalar** instruction) is interpreted as a *hardware
  41 for-loop* that issues **multiple** internal instructions with
  42 sequentially-incrementing register numbers.
  43
  44 Thus it is completely unnecessary to add any vector opcodes - at all -
  45 saving hugely on both hardware and compiler development time when
  46 the concept is dropped on top of a pre-existing ISA.
  47
  48 ## Condition Registers
  49
  50 Branch Facility (Section 2.3.1 V2.07B and V3.0B) has 4-bit registers: CR0 and CR1.  When SimpleV is active, it may be better to set CR6 (the Vector CR field) instead.
  51
  52 ## Carry
  53
  54 SimpleV extends (wraps) *scalar* opcodes with a hardware-level for-loop. Therefore, each scalar operation with a carry-in and carry-out will **require its own carry in and out bit**. Therefore, an extra SPR will be required which allows context switches to save this full set of carry bits.
  55
  56 # Integer Overflow / Saturate
  57
  58 Typically used on vector operations (audio DSP), it makes no sense to have separate opcodes (Opcode 4 SPE).  To be done instead as CSRs / vector-flags on *standard* arithmetic operations.
  59
  60 # atomics
  61
  62 Single instruction on RV, and x86, but multiple on Power. Needs investigation, particularly as to why cache flush exists.
  63
  64 https://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
  65
  66 Hot loops contain significant instruction count, really need new c++11 atomics.  To be proposed as new extension because other OpenPower members will need them too
  67
  68 # FP16
  69
  70 Doesn't exist in Power, need to work out suitable opcodes, basically means duplicating the entire range of FP32/64 ops, symmetrically.
  71
  72 Usually done with a fmt field, 2 bit, last one is FP128
  73
  74 idea: rather than add dozens of new opcodes, add "repurposer" instructions that remap FP32 to 16/32/64/128 and FP64 likewise.  can also be done as C instruction, only needs 4 bits to specify.
  75
  76 # Escape Sequencing
  77
  78 aka "ISAMUX/NS".  Absolutely critical, also to have official endorsement
  79 from OpenPower Foundation.
  80
  81 This will allow extending ISA (see ISAMUX/NS) in a clean fashion
  82 (including for and by OpenPower Foundation)
  83
  84 ## Branches in namespaces
  85
  86 Branches are fine as it is up to the compiler to decide whether to let the
  87 ISAMUX/NS/escape-sequence countdown run out.
  88
  89 This is all a software / compiler / ABI issue.
  90
  91 ## Function calls in namespaces
  92
  93 Storing and restoring the state of the page/subpage CSR should be done by the caller. Or, again, let the countdowns run out.
  94
  95 If certain alternative configs are expected, they are part of the function ABI which must be spec'd.
  96
  97 All of this is a software issue (compiler / ABI).
  98
  99 # Compressed, 48, 64, VBLOCK
 100
 101 TODO investigate Power VLE (Freescale doc Ref 314-68105)
 102
 103 Under Esc Seq, move mulli, twi, tdi out of major OP000 then use the
 104 entire row, 2 bits instead of 3.  greatly simplifies decoder.
 105
 106 * OP 000-000 and 000-001 for 16 bit compressed, 11 bit instructions
 107 * OP 000-010 and 000-011 for 48 bit. 11 bits for SVP P48
 108 * OP 000-100 and 000-201 for 64 bit. 11 bits for SVP P64
 109 * OP 000-110 and 000-111 for VBLOCK. 11 bits available.
 110
 111 # Compressed 16
 112
 113 Further "escape-sequencing".
 114
 115 Only 11 bits available. Idea: have "pages" where one instruction selects
 116 the page number. It also specifies for how long that page is activated
 117 (terminated on a branch)
 118
 119 The length to be a maximum of 4 bits, where 0b1111 indicates "permanently active".
 120
 121 Perhaps split OP000-000 and OP000-001 so that 2 pages can be active.
 122
 123 Store activation length in a CSR.
 124
 125 2nd idea: 11 bits can be used for extremely common operations, then length-encoding page selection for further ops, using the full 16 bit range and an entirely new encoding scheme. 1 bit specifies which of 2 pages was selected?
 126
 127 3rd idea: "stack" mechanism. Allow subpages like a stack, to page in new pages.
 128
 129 3 bits for subpage number. 4 bits for length, gives 7 bits. 4x7 is 28, then 3 bits can be used to specify "stack depth".
 130
 131 Requirements are to have one instruction in each subpage which resets all the way back to PowerISA default. The other is a "back up stack by 1".
 132
 133 # RISCV userspace
 134
 135 Dual ISA, RV userspace only. Requires PowerISA to be able to context-switch RV registers and CSRs.
 136
 137 the exception entry point:
 138 https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/exceptions-64s.S?h=v5.4-rc5#n409
 139
 140 the rest of the context switch code is in a different file:
 141 https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/kernel/entry_64.S?h=v5.4-rc5#n589