pinmux/pinmux_chennai_2018.tex

   1 \documentclass[slidestop]{beamer}
   2 \usepackage{beamerthemesplit}
   3 \usepackage{graphics}
   4 \usepackage{pstricks}
   5
   6 \title{SIMD}
   7 \author{Rishabh Jain}
   8 \author{Luke Kenneth Casson Leighton}
   9
  10
  11 \begin{document}
  12
  13 \frame{
  14    \begin{center}
  15     \huge{Pin Multiplexer}\\
  16     \vspace{32pt}
  17     \Large{Auto-generating documentation, code \\
  18                         and resources for a Pinmux}\\
  19     \vspace{24pt}
  20     \Large{[proposed for] Chennai 9th RISC-V Workshop}\\
  21     \vspace{16pt}
  22     \large{\today}
  23   \end{center}
  24 }
  25
  26
  27 \frame{\frametitle{Credits and Acknowledgements}
  28
  29  \begin{itemize}
  30    \item TODO\vspace{10pt}
  31   \end{itemize}
  32 }
  33
  34
  35 \frame{\frametitle{Glossary}
  36
  37  \begin{itemize}
  38    \item GPIO: general-purpose reconfigureable I/O (Input/Output).
  39    \item Pin: an I/O pad.  May be driven (input) or may drive (output).
  40    \item FN: term for a single-wire "function", such as UART\_TX,
  41              I2C\_SDA, SDMMC\_D0 etc.  may be an input, output or both
  42                  (bi-directional case: two wires are always allocated, one
  43                   for input to the function and one for output from the function).
  44    \item Bus: a group of bi-directional functions (SDMMC D0 to D3)
  45          where the direction is ganged and under the Bus's control
  46    \item Input Priority Muxer: a multiplexer with N selector
  47                  wires and N associated inputs.  The lowest (highest?) indexed
  48                  "selector" enabled results in its
  49                  input being routed to the output.
  50    \item Output Demuxer: a one-to-many "redirector" where a single
  51              input is "routed" to any one output, based
  52              on a selector.
  53   \end{itemize}
  54 }
  55
  56
  57 \frame{\frametitle{Why, How and What is a Pinmux?}
  58
  59  \begin{itemize}
  60    \item Why? To save cost, increase yield, and to target multiple
  61          markets with the same design, thereby increasing uptake
  62          and consequently taking advantage of volume pricing.\vspace{4pt}
  63          \\
  64          Summary: it's all about making more money!\vspace{4pt}
  65    \item How? By multiplexing many more functions (100 to 1,200) than there
  66          are actual available pins (48 to 500), the required chip package
  67              is far less costly and the chip more desirable\vspace{4pt}
  68    \item What? A many-to-many dynamically-configureable router of
  69          I/O functions to I/O pins\vspace{4pt}
  70    \item \bf{Note: actual muxing is deceptively simple, but like
  71          a DRAM cell it's actually about the ancillaries / extras}
  72   \end{itemize}
  73 }
  74
  75
  76 \frame{\frametitle{Associated Extras}
  77
  78  \begin{itemize}
  79    \item Design Specification
  80    \item Scenario analysis (whether the chip will fit "markets")
  81    \item Documentation: Summary sheet, Technical Reference Manual.
  82    \item Test suites
  83    \item Control Interface (AXI4 / Wishbone / TileLink / other)
  84    \item Simulation
  85    \item Linux kernel drivers, DTB, libopencm3, Arduino libraries etc.
  86   \end{itemize}
  87  Example context:
  88  \begin{itemize}
  89    \item Shakti M-Class has 160 pins with a 99.5\% full 4-way mux
  90    \item Almost 640-way routing, 6 "scenarios" (7th TBD),
  91          100+ page Manual needed,
  92          \bf{17,500 lines of auto-generated code}
  93   \end{itemize}
  94 }
  95
  96
  97 \frame{
  98   \vspace{30pt}
  99   \begin{center}
 100     {\Huge
 101                    ALL of these\vspace{20pt}\\
 102                    can be\vspace{20pt}\\
 103                    auto-generated\vspace{30pt}
 104         }
 105         \\
 106         (translation: it would be insanely costly to do them by hand)
 107   \end{center}
 108
 109 }
 110
 111 \frame{\frametitle{Muxer cases to handle}
 112
 113  \begin{itemize}
 114    \item Many FN outputs to Many Pins: no problem\\
 115              (weird configuration by end-user, but no damage to ASIC)\vspace{10pt}
 116    \item One Pin to Many FN inputs: no problem\\
 117          (weird configuration by end-user, but no damage to ASIC)\vspace{10pt}
 118    \item Many Pins to One FN input: {\bf Priority Mux needed}\\
 119              No priority mux: Pin1 = HI, Pin0 = LO, ASIC is damaged\vspace{10pt}
 120    \item Some FNs (I2C\_SDA, SD\_D0..3) are I/O Buses\\
 121              Bi-directional control of the Pin must be handed to the
 122              FN\vspace{10pt}
 123    \item Nice to have: Bus sets pintype, signal strength etc.\vspace{10pt}
 124   \end{itemize}
 125 }
 126
 127
 128 \frame{\frametitle{Pin Configuration, input and output}
 129
 130  In/out:
 131  \begin{itemize}
 132    \item Output-Enable (aka Input disable): switches pad to In or Out
 133    \item Output (actually an input wire controlling pin's level, HI/LO)
 134    \item Input (actually an output wire set based on pin's driven level)
 135  \end{itemize}
 136  Characteristics:
 137  \begin{itemize}
 138    \item Output current level: 10mA / 20mA / 30mA / 40mA
 139    \item Input hysteresis: low / middle / high. Stops signal noise
 140    \item Pin characteristics: CMOS Push-Push / Open-Drain
 141    \item Pull-up enable: built-in 10k (50k?) resistor
 142    \item Pull-down enable: built-in 10k (50k?) resistor
 143    \item Muxing and IRQ Edge-detection not part of the I/O pin
 144   \end{itemize}
 145 }
 146
 147
 148 \frame{\frametitle{Standard GPIO 4-way in/out Mux and I/O pad}
 149  \begin{center}
 150   \includegraphics[height=2.5in]{../shakti/m_class/mygpiomux.jpg}\\
 151   {\bf 4-in, 4-out, pullup/down, hysteresis, edge-detection (EINT)}
 152  \end{center}
 153 }
 154
 155
 156 \frame{\frametitle{Register-to-pad "control" settings}
 157  \begin{center}
 158   \includegraphics[height=2.5in]{reg_gpio_cap_ctrl.jpg}\\
 159   {\bf pullup/down, hysteresis, current, edge-detection}
 160  \end{center}
 161 }
 162
 163
 164 \frame{\frametitle{In/Out muxing, direction control}
 165  \begin{center}
 166   \includegraphics[height=2.5in]{reg_gpio_fn_ctrl.jpg}\\
 167   {\bf Note: function can control I/O direction}
 168  \end{center}
 169 }
 170
 171
 172 \frame{\frametitle{Simplified I/O pad Block Diagram}
 173  \begin{center}
 174   \includegraphics[height=2.5in]{reg_gpio_pinblock.jpg}\\
 175   {\bf 3 wires: IN, OUT, OUTEN (also = !INEN) }
 176  \end{center}
 177 }
 178
 179
 180 \frame{\frametitle{Output (and OUTEN) Wiring. 2 pins, 2 GPIO, 2 Fns}
 181  \begin{center}
 182   \includegraphics[height=2.5in]{reg_gpio_out_wiring.jpg}\\
 183   {\bf Reg0 for Pin0, Reg1 for Pin1, Output and OUTEN same mux }
 184  \end{center}
 185 }
 186
 187
 188 \frame{\frametitle{Input Selection and Priority Muxing}
 189  \begin{center}
 190   \includegraphics[height=0.75in]{reg_gpio_comparator.jpg}\\
 191   {\bf Muxer enables input selection}\\
 192   \vspace{10pt}
 193   \includegraphics[height=1.25in]{reg_gpio_in_prioritymux.jpg}\\
 194   {\bf However multiple inputs must be prioritised }
 195  \end{center}
 196 }
 197
 198
 199 \frame{\frametitle{Input Mux Wiring}
 200  \begin{center}
 201   \includegraphics[height=2.5in]{reg_gpio_in_wiring.jpg}\\
 202   {\bf Pin Mux selection vals NOT same as FN selection vals}
 203  \end{center}
 204 }
 205
 206
 207 \frame{\frametitle{Summary}
 208
 209  \begin{itemize}
 210    \item TODO
 211   \end{itemize}
 212 }
 213
 214
 215 \frame{
 216   \begin{center}
 217     {\Huge The end\vspace{20pt}\\
 218                    Thank you\vspace{20pt}\\
 219                    Questions?\vspace{20pt}
 220         }
 221   \end{center}
 222
 223   \begin{itemize}
 224         \item http://libre-riscv.org/shakti/m\_class/pinmux/
 225   \end{itemize}
 226 }
 227
 228
 229 \end{document}