pinmux/pinmux_chennai_2018.tex

   1 \documentclass[slidestop]{beamer}
   2 \usepackage{beamerthemesplit}
   3 \usepackage{graphics}
   4 \usepackage{pstricks}
   5
   6 \title{SIMD}
   7 \author{Rishabh Jain}
   8 \author{Luke Kenneth Casson Leighton}
   9
  10
  11 \begin{document}
  12
  13 \frame{
  14    \begin{center}
  15     \huge{Pin Multiplexer}\\
  16     \vspace{32pt}
  17     \Large{Auto-generating documentation, code \\
  18                         and resources for a Pinmux}\\
  19     \vspace{24pt}
  20     \Large{[proposed for] Chennai 9th RISC-V Workshop}\\
  21     \vspace{16pt}
  22     \large{\today}
  23   \end{center}
  24 }
  25
  26
  27 \frame{\frametitle{Credits and Acknowledgements}
  28
  29  \begin{itemize}
  30    \item TODO\vspace{10pt}
  31   \end{itemize}
  32 }
  33
  34
  35 \frame{\frametitle{Glossary}
  36
  37  \begin{itemize}
  38    \item Pin: an I/O pad.  May be driven (input) or may drive (output).
  39    \item FN: term for a single-wire "function", such as UART\_TX,
  40              I2C\_SDA, SDMMC\_D0 etc.  may be an input, output or both
  41                  (bi-directional case: two wires are always allocated, one
  42                   for input to the function and one for output from the function).
  43    \item Input Priority Muxer: a multiplexer that has N selector
  44                  wires and N inputs, where the lowest (or highest) indexed
  45                  "selector" that is enabled results in its corresponding
  46                  input being routed to the output.
  47    \item Output Demuxer: a one-to-many "redirector" where a single
  48              input is "routed" to any one of a number of outputs, based
  49              on a selection address.
  50    \item GPIO: general-purpose reconfigureable I/O (Input/Output).
  51   \end{itemize}
  52 }
  53
  54
  55 \frame{\frametitle{Why, How and What is a Pinmux?}
  56
  57  \begin{itemize}
  58    \item Why? To save cost, increase yield, and to target multiple
  59          markets with the same design, thereby increasing uptake
  60          and consequently taking advantage of volume pricing.\vspace{4pt}
  61          \\
  62          Summary: it's all about making more money!\vspace{4pt}
  63    \item How? By multiplexing many more functions (100 to 1,200) than there
  64          are actual available pins (48 to 500), the required chip package
  65              is far less costly and the chip more desirable\vspace{4pt}
  66    \item What? A many-to-many dynamically-configureable router of
  67          I/O functions to I/O pins\vspace{4pt}
  68    \item \bf{Note: actual muxing is deceptively simple, but like
  69          a DRAM cell it's actually about the ancillaries / extras}
  70   \end{itemize}
  71 }
  72
  73
  74 \frame{\frametitle{Associated Extras}
  75
  76  \begin{itemize}
  77    \item Design Specification
  78    \item Scenario analysis (whether the chip will fit "markets")
  79    \item Documentation: Summary sheet, Technical Reference Manual.
  80    \item Test suites
  81    \item Control Interface (AXI4 / Wishbone / TileLink / other)
  82    \item Simulation
  83    \item Linux kernel drivers, DTB, libopencm3, Arduino libraries etc.
  84   \end{itemize}
  85  Example context:
  86  \begin{itemize}
  87    \item Shakti M-Class has 160 pins with a 99.5\% full 4-way mux
  88    \item Almost 640-way routing, 6 "scenarios" (7th TBD),
  89          100+ page Manual needed,
  90          \bf{17,500 lines of auto-generated code}
  91   \end{itemize}
  92 }
  93
  94
  95 \frame{
  96   \vspace{30pt}
  97   \begin{center}
  98     {\Huge
  99                    ALL of these\vspace{20pt}\\
 100                    can be\vspace{20pt}\\
 101                    auto-generated\vspace{30pt}
 102         }
 103         \\
 104         (translation: it would be insanely costly to do them by hand)
 105   \end{center}
 106
 107 }
 108
 109 \frame{\frametitle{Muxer cases to handle}
 110
 111  \begin{itemize}
 112    \item Many FN outputs to Many Pins: no problem\\
 113              (weird configuration by end-user, but no damage to ASIC)\vspace{10pt}
 114    \item One Pin to Many FN inputs: no problem\\
 115          (weird configuration by end-user, but no damage to ASIC)\vspace{10pt}
 116    \item Many Pins to One FN input: {\bf Priority Mux needed}\\
 117              No priority mux: Pin1 = HI, Pin0 = LO, ASIC is damaged\vspace{10pt}
 118    \item Some FNs (I2C\_SDA, SD\_D0..3) are I/O Buses\\
 119              Bi-directional control of the Pin must be handed to the
 120              FN\vspace{10pt}
 121    \item TODO\vspace{10pt}
 122   \end{itemize}
 123 }
 124
 125
 126 \frame{\frametitle{Standard GPIO 4-way in/out Mux and I/O pad}
 127  \begin{center}
 128   \includegraphics[height=2.5in]{../shakti/m_class/mygpiomux.jpg}\\
 129   {\bf 4-in, 4-out, pullup/down, hysteresis, edge-detection (EINT)}
 130  \end{center}
 131 }
 132
 133
 134 \frame{\frametitle{Register-to-pad "control" settings}
 135  \begin{center}
 136   \includegraphics[height=2.5in]{reg_gpio_cap_ctrl.jpg}\\
 137   {\bf pullup/down, hysteresis, current, edge-detection}
 138  \end{center}
 139 }
 140
 141
 142 \frame{\frametitle{In/Out muxing, direction control}
 143  \begin{center}
 144   \includegraphics[height=2.5in]{reg_gpio_fn_ctrl.jpg}\\
 145   {\bf Note: function can control I/O direction}
 146  \end{center}
 147 }
 148
 149
 150 \frame{\frametitle{Simplified I/O pad Block Diagram}
 151  \begin{center}
 152   \includegraphics[height=2.5in]{reg_gpio_pinblock.jpg}\\
 153   {\bf 3 wires: IN, OUT, OUTEN (also = !INEN) }
 154  \end{center}
 155 }
 156
 157
 158 \frame{\frametitle{Output (and OUTEN) Wiring. 2 pins, 2 GPIO, 2 Fns}
 159  \begin{center}
 160   \includegraphics[height=2.5in]{reg_gpio_out_wiring.jpg}\\
 161   {\bf Reg0 for Pin0, Reg1 for Pin1, Output and OUTEN same mux }
 162  \end{center}
 163 }
 164
 165
 166 \frame{\frametitle{Input Selection and Priority Muxing}
 167  \begin{center}
 168   \includegraphics[height=0.75in]{reg_gpio_comparator.jpg}\\
 169   {\bf Muxer enables input selection}\\
 170   \vspace{10pt}
 171   \includegraphics[height=1.25in]{reg_gpio_in_prioritymux.jpg}\\
 172   {\bf However multiple inputs must be prioritised }
 173  \end{center}
 174 }
 175
 176
 177 \frame{\frametitle{Input Mux Wiring}
 178  \begin{center}
 179   \includegraphics[height=2.5in]{reg_gpio_in_wiring.jpg}\\
 180   {\bf Pin Mux selection vals NOT same as FN selection vals}
 181  \end{center}
 182 }
 183
 184
 185 \frame{\frametitle{Summary}
 186
 187  \begin{itemize}
 188    \item TODO
 189   \end{itemize}
 190 }
 191
 192
 193 \frame{
 194   \begin{center}
 195     {\Huge The end\vspace{20pt}\\
 196                    Thank you\vspace{20pt}\\
 197                    Questions?\vspace{20pt}
 198         }
 199   \end{center}
 200
 201   \begin{itemize}
 202         \item http://libre-riscv.org/shakti/m\_class/pinmux/
 203   \end{itemize}
 204 }
 205
 206
 207 \end{document}