pinmux/pinmux_chennai_2018.tex

   1 \documentclass[slidestop]{beamer}
   2 \usepackage{beamerthemesplit}
   3 \usepackage{graphics}
   4 \usepackage{pstricks}
   5
   6 \title{SIMD}
   7 \author{Rishabh Jain}
   8 \author{Luke Kenneth Casson Leighton}
   9
  10
  11 \begin{document}
  12
  13 \frame{
  14    \begin{center}
  15     \huge{Pin Multiplexer}\\
  16     \vspace{32pt}
  17     \Large{Auto-generating documentation, code \\
  18                         and resources for a Pinmux}\\
  19     \vspace{24pt}
  20     \Large{[proposed for] Chennai 9th RISC-V Workshop}\\
  21     \vspace{16pt}
  22     \large{\today}
  23   \end{center}
  24 }
  25
  26
  27 \frame{\frametitle{Credits and Acknowledgements}
  28
  29  \begin{itemize}
  30    \item TODO\vspace{10pt}
  31   \end{itemize}
  32 }
  33
  34
  35 \frame{\frametitle{Glossary}
  36
  37  \begin{itemize}
  38    \item Pin: an I/O pad.  May be driven (input) or may drive (output).
  39    \item FN: term for a single-wire "function", such as UART\_TX,
  40              I2C\_SDA, SDMMC\_D0 etc.  may be an input, output or both
  41                  (bi-directional case: two wires are always allocated, one
  42                   for input to the function and one for output from the function).
  43    \item Input Priority Muxer: a multiplexer that has N selector
  44                  wires and N inputs, where the lowest (or highest) indexed
  45                  "selector" that is enabled results in its corresponding
  46                  input being routed to the output.
  47    \item Output Demuxer: a one-to-many "redirector" where a single
  48              input is "routed" to any one of a number of outputs, based
  49              on a selection address.
  50    \item GPIO: general-purpose reconfigureable I/O (Input/Output).
  51   \end{itemize}
  52 }
  53
  54
  55 \frame{\frametitle{Why, How and What is a Pinmux?}
  56
  57  \begin{itemize}
  58    \item Why? To save cost, increase yield, and to target multiple
  59          markets with the same design, thereby increasing uptake
  60          and consequently taking advantage of volume pricing.\vspace{10pt}
  61          \\
  62          Summary: it's all about making more money!\vspace{10pt}
  63    \item How? By multiplexing many more functions (100 to 1,200) than there
  64          are actual available pins (48 to 500), the required chip package
  65              is far less costly and the chip more desirable\vspace{10pt}
  66    \item What? A many-to-many dynamically-configureable router of
  67          I/O functions to I/O pins\vspace{10pt}
  68   \end{itemize}
  69 }
  70
  71
  72 \frame{\frametitle{Muxer cases to handle}
  73
  74  \begin{itemize}
  75    \item Many FN outputs to Many Pins: no problem\\
  76              (weird configuration by end-user, but no damage to ASIC)\vspace{10pt}
  77    \item One Pin to Many FN inputs: no problem\\
  78          (weird configuration by end-user, but no damage to ASIC)\vspace{10pt}
  79    \item Many Pins to One FN input: {\bf Priority Mux needed}\\
  80              No priority mux: Pin1 = HI, Pin0 = LO, ASIC is damaged\vspace{10pt}
  81    \item Some FNs (I2C\_SDA, SD\_D0..3) are I/O Buses\\
  82              Bi-directional control of the Pin must be handed to the
  83              FN\vspace{10pt}
  84    \item TODO\vspace{10pt}
  85   \end{itemize}
  86 }
  87
  88
  89 \frame{\frametitle{Standard GPIO 4-way in/out Mux and I/O pad}
  90  \begin{center}
  91   \includegraphics[height=2.5in]{../shakti/m_class/mygpiomux.jpg}\\
  92   {\bf 4-in, 4-out, pullup/down, hysteresis, edge-detection (EINT)}
  93  \end{center}
  94 }
  95
  96
  97 \frame{\frametitle{Register-to-pad "control" settings}
  98  \begin{center}
  99   \includegraphics[height=2.5in]{reg_gpio_cap_ctrl.jpg}\\
 100   {\bf pullup/down, hysteresis, current, edge-detection}
 101  \end{center}
 102 }
 103
 104
 105 \frame{\frametitle{In/Out muxing, direction control}
 106  \begin{center}
 107   \includegraphics[height=2.5in]{reg_gpio_fn_ctrl.jpg}\\
 108   {\bf Note: function can control I/O direction}
 109  \end{center}
 110 }
 111
 112
 113 \frame{\frametitle{Simplified I/O pad Block Diagram}
 114  \begin{center}
 115   \includegraphics[height=2.5in]{reg_gpio_pinblock.jpg}\\
 116   {\bf 3 wires: IN, OUT, OUTEN (also = !INEN) }
 117  \end{center}
 118 }
 119
 120
 121 \frame{\frametitle{Output (and OUTEN) Wiring. 2 pins, 2 GPIO, 2 Fns}
 122  \begin{center}
 123   \includegraphics[height=2.5in]{reg_gpio_out_wiring.jpg}\\
 124   {\bf Reg0 for Pin0, Reg1 for Pin1, Output and OUTEN same mux }
 125  \end{center}
 126 }
 127
 128
 129 \frame{\frametitle{Input Selection and Priority Muxing}
 130  \begin{center}
 131   \includegraphics[height=0.75in]{reg_gpio_comparator.jpg}\\
 132   {\bf Muxer enables input selection}\\
 133   \vspace{10pt}
 134   \includegraphics[height=1.25in]{reg_gpio_in_prioritymux.jpg}\\
 135   {\bf However multiple inputs must be prioritised }
 136  \end{center}
 137 }
 138
 139
 140 \frame{\frametitle{Input Mux Wiring}
 141  \begin{center}
 142   \includegraphics[height=2.5in]{reg_gpio_in_wiring.jpg}\\
 143   {\bf Pin Mux selection vals NOT same as FN selection vals}
 144  \end{center}
 145 }
 146
 147
 148 \frame{\frametitle{Summary}
 149
 150  \begin{itemize}
 151    \item TODO
 152   \end{itemize}
 153 }
 154
 155
 156 \frame{
 157   \begin{center}
 158     {\Huge The end\vspace{20pt}\\
 159                    Thank you\vspace{20pt}\\
 160                    Questions?\vspace{20pt}
 161         }
 162   \end{center}
 163
 164   \begin{itemize}
 165         \item http://libre-riscv.org/shakti/m\_class/pinmux/
 166   \end{itemize}
 167 }
 168
 169
 170 \end{document}