1 # Resources and Specifications
3 This page aims to collect all the resources and specifications we need
4 in one place for quick access. We will try our best to keep links here
5 up-to-date. Feel free to add more links here.
11 This section is primarily a series of useful links found online
13 * [FSiC2019](https://wiki.f-si.org/index.php/FSiC2019)
14 * Fundamentals to learn to get started [[3d_gpu/tutorial]]
16 ## Is Open Source Hardware Profitable?
17 [RaptorCS on FOSS Hardware Interview](https://www.youtube.com/watch?v=o5Ihqg72T3c&feature=youtu.be)
21 * [3.0 PDF](https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0)
22 * [2.07 PDF](https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b)
23 * Virginia Tech course <https://github.com/w-feng/CompArch-MIPS-POWER>
25 ## Overview of the user ISA:
27 * [Raymond Chen's PowerPC series](https://devblogs.microsoft.com/oldnewthing/20180806-00/?p=99425)
28 * Power ISA listings <https://power-isa-beta.mybluemix.net/>
30 ## OpenPOWER OpenFSI Spec (2016)
32 * [OpenPOWER OpenFSI Spec](http://openpowerfoundation.org/wp-content/uploads/resources/OpenFSI-spec-100/OpenFSI-spec-20161212.pdf)
34 * [OpenPOWER OpenFSI Compliance Spec](http://openpowerfoundation.org/wp-content/uploads/resources/openpower-fsi-thts-1.0/openpower-fsi-thts-20180130.pdf)
36 # Energy-efficient cores
38 * https://arxiv.org/abs/2002.10143
40 # Open Access Publication locations
42 * <https://open-research-europe.ec.europa.eu/browse/engineering-and-technology>
46 * <https://www.reddit.com/r/OpenPOWER/>
47 * <http://lists.mailinglist.openpowerfoundation.org/pipermail/openpower-hdl-cores/>
48 * <http://lists.mailinglist.openpowerfoundation.org/pipermail/openpower-community-dev/>
49 * Open tape-out mailing list <https://groups.google.com/a/opentapeout.dev/g/mailinglist>
53 * EABI 1.9 supplement <https://refspecs.linuxfoundation.org/ELF/ppc64/PPC-elf64abi-1.9.html>
54 * https://refspecs.linuxfoundation.org/ELF/ppc64/PPC-elf64abi-1.9.pdf
58 * <https://www.tdx.cat/bitstream/handle/10803/674224/TCRL1de1.pdf> Vector registers may be
59 made "ultra-wide" (SX Aurora / Cray)
61 # Other GPU Specifications
64 * https://developer.amd.com/wp-content/resources/RDNA_Shader_ISA.pdf
65 * https://developer.amd.com/wp-content/resources/Vega_Shader_ISA_28July2017.pdf
67 * [Nyuzi](https://github.com/jbush001/NyuziProcessor)
73 * [Useful JTAG implementation reference: Design Of IEEE 1149.1 TAP Controller IP Core by Shelja, Nandakumar and Muruganantham, DOI:10.5121/csit.2016.60910](https://web.archive.org/web/20201021174944/https://airccj.org/CSCP/vol6/csit65610.pdf)
77 "The objective of this work is to design and implement a TAP controller IP core compatible with IEEE 1149.1-2013 revision of the standard. The test logic architecture also includes the Test Mode Persistence controller and its associated logic. This work is expected to serve as a ready to use module that can be directly inserted in to a new digital IC designs with little modifications."
80 - [Qemu emulation](https://github.com/qemu/qemu/commit/d5fee0bbe68d5e61e2d2beb5ff6de0b9c1cfd182)
84 - [A Primer on Memory Consistency and Cache Coherence
85 ](https://www.morganclaypool.com/doi/10.2200/S00962ED2V01Y201910CAC049)
87 ## D-Cache Possible Optimizations papers and links
88 - [ACDC: Small, Predictable and High-Performance Data Cache](https://dl.acm.org/doi/10.1145/2677093)
89 - [Stop Crying Over Your Cache Miss Rate: Handling Efficiently Thousands of
90 Outstanding Misses in FPGAs](https://dl.acm.org/doi/abs/10.1145/3289602.3293901)
92 # BW Enhancing Shared L1 Cache Design research done in cooperation with AMD
93 - [Youtube video PACT 2020 - Analyzing and Leveraging Shared L1 Caches in GPUs](https://m.youtube.com/watch?v=CGIhOnt7F6s)
94 - [Url to PDF of paper on author's website (clicking will download the pdf)](https://adwaitjog.github.io/docs/pdf/sharedl1-pact20.pdf)
97 # RTL Arithmetic SQRT, FPU etc.
99 ## Wallace vs Dadda Multipliers
101 * [Paper comparing efficiency of Wallace and Dadda Multipliers in RTL implementations (clicking will download the pdf from archive.org)](https://web.archive.org/web/20180717013227/http://ieeemilestones.ethw.org/images/d/db/A_comparison_of_Dadda_and_Wallace_multiplier_delays.pdf)
104 * [Fast Floating Point Square Root](https://pdfs.semanticscholar.org/5060/4e9aff0e37089c4ab9a376c3f35761ffe28b.pdf)
105 * [Reciprocal Square Root Algorithm](http://www.acsel-lab.com/arithmetic/arith15/papers/ARITH15_Takagi.pdf)
106 * [Fast Calculation of Cube and Inverse Cube Roots Using a Magic Constant and Its Implementation on Microcontrollers (clicking will download the pdf)](https://res.mdpi.com/d_attachment/energies/energies-14-01058/article_deploy/energies-14-01058-v2.pdf)
107 * [Modified Fast Inverse Square Root and Square Root Approximation Algorithms: The Method of Switching Magic Constants (clicking will download the pdf)](https://res.mdpi.com/d_attachment/computation/computation-09-00021/article_deploy/computation-09-00021-v3.pdf)
110 ## CORDIC and related algorithms
112 * <https://bugs.libre-soc.org/show_bug.cgi?id=127> research into CORDIC
113 * <https://bugs.libre-soc.org/show_bug.cgi?id=208>
114 * [BKM (log(x) and e^x)](https://en.wikipedia.org/wiki/BKM_algorithm)
115 * [CORDIC](http://www.andraka.com/files/crdcsrvy.pdf)
116 - Does not have an easy way of computing tan(x)
117 * [zipcpu CORDIC](https://zipcpu.com/dsp/2017/08/30/cordic.html)
118 * [Low latency and Low error floating point TCORDIC](https://ieeexplore.ieee.org/document/7784797) (email Michael or Cole if you don't have IEEE access)
119 * <http://www.myhdl.org/docs/examples/sinecomp/> MyHDL version of CORDIC
120 * <https://dspguru.com/dsp/faqs/cordic/>
122 ## IEEE Standard for Floating-Point Arithmetic (IEEE 754)
124 Almost all modern computers follow the IEEE Floating-Point Standard. Of
125 course, we will follow it as well for interoperability.
127 * IEEE 754-2019: <https://standards.ieee.org/standard/754-2019.html>
129 Note: Even though this is such an important standard used by everyone,
130 it is unfortunately not freely available and requires a payment to
131 access. However, each of the Libre-SOC members already have access
134 * [Lecture notes - Floating Point Appreciation](http://pages.cs.wisc.edu/~markhill/cs354/Fall2008/notes/flpt.apprec.html)
136 Among other things, has a nice explanation on arithmetic, rounding modes and the sticky bit.
138 * [What Every Computer Scientist Should Know About Floating-Point Arithmetic](https://docs.oracle.com/cd/E19957-01/806-3568/ncg_goldberg.html)
140 Nice resource on rounding errors (ulps and epsilon) and the "table maker's dilemma".
142 ## Past FPU Mistakes to learn from
144 * [Intel Underestimates Error Bounds by 1.3 quintillion on
145 Random ASCII – tech blog of Bruce Dawson ](https://randomascii.wordpress.com/2014/10/09/intel-underestimates-error-bounds-by-1-3-quintillion/)
146 * [Intel overstates FPU accuracy 06/01/2013](http://notabs.org/fpuaccuracy)
147 * How not to design an ISA
148 <https://player.vimeo.com/video/450406346>
149 Meester Forsyth <http://eelpi.gotdns.org/>
153 The Khronos Group creates open standards for authoring and acceleration
154 of graphics, media, and computation. It is a requirement for our hybrid
155 CPU/GPU to be compliant with these standards *as well* as with IEEE754,
156 in order to be commercially-competitive in both areas: especially Vulkan
157 and OpenCL being the most important. SPIR-V is also important for the
160 Thus the [[zfpacc_proposal]] has been created which permits runtime dynamic
161 switching between different accuracy levels, in userspace applications.
163 [**SPIR-V Main Page Link**](https://www.khronos.org/registry/spir-v/)
165 * [SPIR-V 1.5 Specification Revision 1](https://www.khronos.org/registry/spir-v/specs/unified1/SPIRV.html)
166 * [SPIR-V OpenCL Extended Instruction Set](https://www.khronos.org/registry/spir-v/specs/unified1/OpenCL.ExtendedInstructionSet.100.html)
167 * [SPIR-V GLSL Extended Instruction Set](https://www.khronos.org/registry/spir-v/specs/unified1/GLSL.std.450.html)
169 [**Vulkan Main Page Link**](https://www.khronos.org/registry/vulkan/)
171 * [Vulkan 1.1.122](https://www.khronos.org/registry/vulkan/specs/1.1-extensions/html/index.html)
173 [**OpenCL Main Page**](https://www.khronos.org/registry/OpenCL/)
175 * [OpenCL 2.2 API Specification](https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_API.html)
176 * [OpenCL 2.2 Extension Specification](https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_Ext.html)
177 * [OpenCL 2.2 SPIR-V Environment Specification](https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_Env.html)
179 * OpenCL released the proposed OpenCL 3.0 spec for comments in april 2020
181 * [Announcement video](https://youtu.be/h0_syTg6TtY)
182 * [Announcement video slides (PDF)](https://www.khronos.org/assets/uploads/apis/OpenCL-3.0-Launch-Apr20.pdf)
184 Note: We are implementing hardware accelerated Vulkan and
185 OpenCL while relying on other software projects to translate APIs to
186 Vulkan. E.g. Zink allows for OpenGL-to-Vulkan in software.
188 # Open Source (CC BY + MIT) DirectX specs (by Microsoft, but not official specs)
190 https://github.com/Microsoft/DirectX-Specs
192 # Graphics and Compute API Stack
194 I found this informative post that mentions Kazan and a whole bunch of
195 other stuff. It looks like *many* APIs can be emulated on top of Vulkan,
196 although performance is not evaluated.
198 <https://synappsis.wordpress.com/2017/06/03/opengl-over-vulkan-dev/>
200 * Pixilica is heading up an initiative to create a RISC-V graphical ISA
202 * [Pixilica 3D Graphical ISA Slides](https://b5792ddd-543e-4dd4-9b97-fe259caf375d.filesusr.com/ugd/841f2a_c8685ced353b4c3ea20dbb993c4d4d18.pdf)
204 # 3D Graphics Texture compression software and hardware
206 * [Proprietary Rad Game Tools Oddle Texture Software Compression](https://web.archive.org/web/20200913122043/http://www.radgametools.com/oodle.htm)
208 * [Blog post by one of the engineers who developed the proprietary Rad Game Tools Oddle Texture Software Compression and the Oodle Kraken decompression software and hardware decoder used in the ps5 ssd](https://archive.vn/oz0pG)
210 # Various POWER Communities
211 - [An effort to make a 100% Libre POWER Laptop](https://www.powerpc-notebook.org/en/)
212 The T2080 is a POWER8 chip.
213 - [Power Progress Community](https://www.powerprogress.org/campaigns/donations-to-all-the-power-progress-community-projects/)
214 Supporting/Raising awareness of various POWER related open projects on the FOSS
216 - [OpenPOWER](https://openpowerfoundation.org)
217 Promotes and ensure compliance with the Power ISA amongst members.
218 - [OpenCapi](https://opencapi.org)
219 High performance interconnect for POWER machines. One of the big advantages
220 of the POWER architecture. Notably more performant than PCIE Gen4, and is
221 designed to be layered on top of the physical PCIE link.
222 - [OpenPOWER “Virtual Coffee” Calls](https://openpowerfoundation.org/openpower-virtual-coffee-calls/)
223 Truly open bi-weekly teleconference lines for anybody interested in helping
224 advance or adopting the POWER architecture.
233 * LIP6's Coriolis - a set of backend design tools:
234 <https://www-soc.lip6.fr/equipe-cian/logiciels/coriolis/>
236 Note: The rest of LIP6's website is in French, but there is a UK flag
237 in the corner that gives the English version.
239 # Logical Equivalence and extraction
242 * CVC https://github.com/d-m-bailey/cvc
246 * KLayout - Layout viewer and editor: <https://www.klayout.de/>
250 * https://nazca-design.org/convert-image-to-gds/
252 # The OpenROAD Project
254 OpenROAD seeks to develop and foster an autonomous, 24-hour, open-source
255 layout generation flow (RTL-to-GDS).
257 * <https://theopenroadproject.org/>
259 # Other RISC-V GPU attempts
261 * <https://fossi-foundation.org/2019/09/03/gsoc-64b-pointers-in-rv32>
263 * <http://bjump.org/manycore/>
265 * <https://resharma.github.io/RISCV32-GPU/>
267 TODO: Get in touch and discuss collaboration
269 # Tests, Benchmarks, Conformance, Compliance, Verification, etc.
273 RISC-V Foundation is in the process of creating an official conformance
274 test. It's still in development as far as I can tell.
276 * //TODO LINK TO RISC-V CONFORMANCE TEST
278 ## IEEE 754 Testing/Emulation
280 IEEE 754 has no official tests for floating-point but there are
281 well-known third party tools to check such as John Hauser's TestFloat.
283 There is also his SoftFloat library, which is a software emulation
284 library for IEEE 754.
286 * <http://www.jhauser.us/arithmetic/>
288 Jacob is also working on an IEEE 754 software emulation library written
289 in Rust which also has Python bindings:
291 * Source: <https://salsa.debian.org/Kazan-team/simple-soft-float>
292 * Crate: <https://crates.io/crates/simple-soft-float>
293 * Autogenerated Docs: <https://docs.rs/simple-soft-float/>
295 A cool paper I came across in my research is "IeeeCC754++ : An Advanced
296 Set of Tools to Check IEEE 754-2008 Conformity" by Dr. Matthias Hüsken.
298 * Direct link to PDF:
299 <http://elpub.bib.uni-wuppertal.de/servlets/DerivateServlet/Derivate-7505/dc1735.pdf>
303 OpenCL Conformance Tests
305 * <https://github.com/KhronosGroup/OpenCL-CTS>
307 Vulkan Conformance Tests
309 * <https://github.com/KhronosGroup/VK-GL-CTS>
311 MAJOR NOTE: We are **not** allowed to say we are compliant with any of
312 the Khronos standards until we actually make an official submission,
313 do the paperwork, and pay the relevant fees.
315 ## Formal Verification
317 Formal verification of Libre RISC-V ensures that it is bug-free in
318 regards to what we specify. Of course, it is important to do the formal
319 verification as a final step in the development process before we produce
320 thousands or millions of silicon.
322 * Possible way to speed up our solvers for our formal proofs <https://web.archive.org/web/20201029205507/https://github.com/eth-sri/fastsmt>
324 * Algorithms (papers) submitted for 2018 International SAT Competition <https://web.archive.org/web/20201029205239/https://helda.helsinki.fi/bitstream/handle/10138/237063/sc2018_proceedings.pdf> <https://web.archive.org/web/20201029205637/http://www.satcompetition.org/>
325 * Minisail <https://www.isa-afp.org/entries/MiniSail.html> - compiler
328 Some learning resources I found in the community:
330 * ZipCPU: <http://zipcpu.com/> ZipCPU provides a comprehensive
331 tutorial for beginners and many exercises/quizzes/slides:
332 <http://zipcpu.com/tutorial/>
333 * Western Digital's SweRV CPU blog (I recommend looking at all their
334 posts): <https://tomverbeure.github.io/>
335 * <https://tomverbeure.github.io/risc-v/2018/11/19/A-Bug-Free-RISC-V-Core-without-Simulation.html>
336 * <https://tomverbeure.github.io/rtl/2019/01/04/Under-the-Hood-of-Formal-Verification.html>
340 * Formal verification of a fully IEEE compliant floating point unit
341 <https://publikationen.sulb.uni-saarland.de/bitstream/20.500.11880/25760/1/ChristianJacobi_ProfDrWolfgangJPaul.pdf>
342 * <https://www-wjp.cs.uni-sb.de/forschung/projekte/VAMP/?lang=en>
343 * the PVS/hw subfolder is under the 2-clause BSD license:
344 <https://www-wjp.cs.uni-sb.de/forschung/projekte/VAMP/PVS/hw/COPYRIGHT>
345 * <https://alastairreid.github.io/RelatedWork/papers/beyer:ijsttt:2006/>
349 * <https://www.ohwr.org/project/wishbone-gen>
353 * Avalon <https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf>
354 * CXM <https://www.computeexpresslink.org/download-the-specification>
358 * THOR <https://github.com/robfinch/Thor/blob/main/Thor2021/doc/Thor2021.pdf>
361 * MRISC32 <https://github.com/mrisc32/mrisc32>
365 ## Adding new instructions:
367 * <https://archive.fosdem.org/2015/schedule/event/llvm_internal_asm/>
371 * <https://danluu.com/branch-prediction/>
375 * <https://ieeexplore.ieee.org/document/9591456> pylog fpga
376 <https://github.com/hst10/pylog>
377 * [Migen - a Python RTL](https://jeffrey.co.in/blog/2014/01/d-flip-flop-using-migen/)
378 * [Migen Tutorial](http://blog.lambdaconcept.com/doku.php?id=migen:tutorial>)
379 * There is a great guy, Robert Baruch, who has a good
380 [tutorial](https://github.com/RobertBaruch/nmigen-tutorial) on nMigen.
381 He also build an FPGA-proven Motorola 6800 CPU clone with nMigen and put
382 [the code](https://github.com/RobertBaruch/n6800) and
383 [instructional videos](https://www.youtube.com/playlist?list=PLEeZWGE3PwbbjxV7_XnPSR7ouLR2zjktw)
385 There is now a page [[docs/learning_nmigen]].
386 * [Using our Python Unit Tests(old)](http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-March/000705.html)
387 * <https://chisel.eecs.berkeley.edu/api/latest/chisel3/util/DecoupledIO.html>
391 * <https://github.com/chrische-xx/mpw7> 10-bit SAR ADC
392 * Cray-1 Pocket Reference
393 <https://nitter.it/aka_pugs/status/1546576975166201856>
394 <https://ftp.libre-soc.org/cray-1-pocket-ref/>
395 <https://www.computerhistory.org/collections/catalog/102685876>
396 * <https://github.com/tdene/synth_opt_adders> Prefix-tree generation scripts
397 * <https://debugger.medium.com/why-is-apples-m1-chip-so-fast-3262b158cba2> N1
398 * <https://codeberg.org/tok/librecell> Libre Cell Library
399 * <https://wiki.f-si.org/index.php/FSiC2019>
400 * <https://fusesoc.net>
401 * <https://www.lowrisc.org/open-silicon/>
402 * <http://fpgacpu.ca/fpga/Pipeline_Skid_Buffer.html> pipeline skid buffer
403 * <https://pyvcd.readthedocs.io/en/latest/vcd.gtkw.html> GTKwave
404 * <https://github.com/Ben1152000/sootty> - console-based vcd viewer
405 * <https://github.com/ics-jku/wal> - Waveform Analysis
406 * <http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets.pdf>
407 Synchronous Resets? Asynchronous Resets? I am so confused! How will I
408 ever know which to use? by Clifford E. Cummings
409 * <http://www.sunburst-design.com/papers/CummingsSNUG2008Boston_CDC.pdf>
410 Clock Domain Crossing (CDC) Design & Verification Techniques Using
411 SystemVerilog, by Clifford E. Cummings
412 In particular, see section 5.8.2: Multi-bit CDC signal passing using
413 1-deep / 2-register FIFO synchronizer.
414 * <http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-2016-143.pdf>
415 Understanding Latency Hiding on GPUs, by Vasily Volkov
416 * Efabless "Openlane" <https://github.com/efabless/openlane>
417 * example of openlane with nmigen
418 <https://github.com/lethalbit/nmigen/tree/openlane>
419 * Co-simulation plugin for verilator, transferring to ECP5
420 <https://github.com/vmware/cascade>
421 * Multi-read/write ported memories
422 <https://tomverbeure.github.io/2019/08/03/Multiport-Memories.html>
423 * Data-dependent fail-on-first aka "Fault-tolerant speculative vectorisation"
424 <https://arxiv.org/pdf/1803.06185.pdf>
425 * OpenPOWER Foundation Membership
426 <https://openpowerfoundation.org/membership/how-to-join/membership-kit-9-27-16-4/>
427 * Clock switching (and formal verification)
428 <https://zipcpu.com/formal/2018/05/31/clkswitch.html>
429 * Circuit of Compunit <http://home.macintosh.garden/~mepy2/libre-soc/comp_unit_req_rel.html>
430 * Circuitverse 16-bit <https://circuitverse.org/users/17603/projects/54486>
431 * Nice example model of a Tomasulo-based architecture, with multi-issue, in-order issue, out-of-order execution, in-order commit, with reservation stations and reorder buffers, and hazard avoidance.
432 <https://www.brown.edu/Departments/Engineering/Courses/En164/Tomasulo_10.pdf>
433 * adrian_b architecture comparison <https://news.ycombinator.com/item?id=24459041>
434 * ericandecscent RISC-V <https://libre-soc.org/irclog/%23libre-soc.2021-07-11.log.html>
436 # Real/Physical Projects
438 * [Samuel's KC5 code](http://chiselapp.com/user/kc5tja/repository/kestrel-3/dir?ci=6c559135a301f321&name=cores/cpu)
439 * <https://chips4makers.io/blog/>
440 * <https://hackaday.io/project/7817-zynqberry>
441 * <https://github.com/efabless/raven-picorv32>
442 * <https://efabless.com>
443 * <https://efabless.com/design_catalog/default>
444 * <https://wiki.f-si.org/index.php/The_Raven_chip:_First-time_silicon_success_with_qflow_and_efabless>
445 * <https://mshahrad.github.io/openpiton-asplos16.html>
447 # ASIC tape-out pricing
449 * <https://europractice-ic.com/wp-content/uploads/2020/05/General-MPW-EUROPRACTICE-200505-v8.pdf>
453 * <https://toyota-ai.ventures/>
454 * [NLNet Applications](http://bugs.libre-riscv.org/buglist.cgi?columnlist=assigned_to%2Cbug_status%2Cresolution%2Cshort_desc%2Ccf_budget&f1=cf_nlnet_milestone&o1=equals&query_format=advanced&resolution=---&v1=NLnet.2019.02)
456 # Good Programming/Design Practices
458 * [Liskov Substitution Principle](https://en.wikipedia.org/wiki/Liskov_substitution_principle)
459 * [Principle of Least Astonishment](https://en.wikipedia.org/wiki/Principle_of_least_astonishment)
460 * <https://peertube.f-si.org/videos/watch/379ef007-40b7-4a51-ba1a-0db4f48e8b16>
461 * [Rust-Lang Philosophy and Consensus](http://smallcultfollowing.com/babysteps/blog/2019/04/19/aic-adventures-in-consensus/)
463 * <https://youtu.be/o5Ihqg72T3c>
464 * <http://flopoco.gforge.inria.fr/>
465 * Fundamentals of Modern VLSI Devices
466 <https://groups.google.com/a/groups.riscv.org/d/msg/hw-dev/b4pPvlzBzu0/7hDfxArEAgAJ>
470 * <https://www.crnhq.org/cr-kit/>
474 * <https://github.com/Isotel/mixedsim>
475 * <http://www.vlsiacademy.org/open-source-cad-tools.html>
476 * <http://ngspice.sourceforge.net/adms.html>
477 * <https://en.wikipedia.org/wiki/Verilog-AMS#Open_Source_Implementations>
479 # Libre-SOC Standards
481 This list auto-generated from a page tag "standards":
483 [[!inline pages="tagged(standards)" actions="no" archive="yes" quick="yes"]]
487 * [[resources/server-setup/web-server]]
488 * [[resources/server-setup/git-mirroring]]
489 * [[resources/server-setup/nagios-monitoring]]
493 * <https://www.fed4fire.eu/testbeds/>
495 # Really Useful Stuff
497 * <https://github.com/im-tomu/fomu-workshop/blob/master/docs/requirements.txt>
498 * <https://github.com/im-tomu/fomu-workshop/blob/master/docs/conf.py#L39-L47>
502 * https://store.digilentinc.com/pmod-sf3-32-mb-serial-nor-flash/
503 * https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists/
504 * https://store.digilentinc.com/pmod-vga-video-graphics-array/
505 * https://store.digilentinc.com/pmod-microsd-microsd-card-slot/
506 * https://store.digilentinc.com/pmod-rtcc-real-time-clock-calendar/
507 * https://store.digilentinc.com/pmod-i2s2-stereo-audio-input-and-output/
509 # CircuitJS experiments
511 * [[resources/high-speed-serdes-in-circuitjs]]
514 * <https://github.com/dkilfoyle/logic2>
515 [Live web version](https://dkilfoyle.github.io/logic2/)
518 > 1. Micro-subset verilog-like DSL for coding the array of logic gates (parsed using Antlr)
519 > 2. Monaco-based code editor with automatic linting/error reporting, smart indentation, code folding, hints
520 > 3. IDE docking ui courtesy of JupyterLab's Lumino widgets
521 > 4. Schematic visualisation courtesy of d3-hwschematic
522 > 5. Testbench simulation with graphical trace output and schematic animation
523 > 6. Circuit description as gates, boolean logic or verilog behavioural model
524 > 7. Generate arbitrary outputs from truth table and Sum of Products or Karnaugh Map
526 [from the GitHub page. As of 2021/03/29]
528 # ASIC Timing and Design flow resources
530 * <https://www.linkedin.com/pulse/asic-design-flow-introduction-timing-constraints-mahmoud-abdellatif/>
531 * <https://www.icdesigntips.com/2020/10/setup-and-hold-time-explained.html>
532 * <https://www.vlsiguide.com/2018/07/clock-tree-synthesis-cts.html>
533 * <https://en.wikipedia.org/wiki/Frequency_divider>
535 # Geometric Haskell Library
537 * <https://github.com/julialongtin/hslice/blob/master/Graphics/Slicer/Math/GeometricAlgebra.hs>
538 * <https://github.com/julialongtin/hslice/blob/master/Graphics/Slicer/Math/PGA.hs>
539 * <https://arxiv.org/pdf/1501.06511.pdf>
540 * <https://bivector.net/index.html>
542 # Handy Compiler Algorithms for SimpleV
544 Requires aligned registers:
545 * [Graph Coloring Register Allocation for Processors with Multi-Register Operands](https://dl.acm.org/doi/pdf/10.1145/93548.93552)
547 * [Retargetable Graph-Coloring Register Allocation for Irregular Architectures](https://user.it.uu.se/~svenolof/wpo/AllocSCOPES2003.20030626b.pdf)
552 https://www.nextplatform.com/2022/08/22/the-expanding-cxl-memory-hierarchy-is-inevitable-and-good-enough/
553 https://github.com/idea-fasoc/OpenFASOC
554 https://www.quicklogic.com/2020/06/18/the-tipping-point/
555 https://www.quicklogic.com/blog/
556 https://www.quicklogic.com/2020/09/15/why-open-source-ecosystems-make-good-business-sense/
557 https://www.quicklogic.com/qorc/
558 https://en.wikipedia.org/wiki/RAD750
559 The RAD750 system has a price that is comparable to the RAD6000, the latter of which as of 2002 was listed at US$200,000 (equivalent to $284,292 in 2019).
560 https://theamphour.com/525-open-fpga-toolchains-and-machine-learning-with-brian-faith-of-quicklogic/
561 https://github.blog/2021-03-22-open-innovation-winning-strategy-digital-sovereignty-human-progress/
562 https://github.com/olofk/edalize
563 https://github.com/hdl/containers
564 https://twitter.com/OlofKindgren/status/1374848733746192394
565 You might also want to check out https://umarcor.github.io/osvb/index.html
566 https://www.linkedin.com/pulse/1932021-python-now-replaces-tcl-all-besteda-apis-avidan-efody/
567 “TCL has served us well, over the years, allowing us to provide an API, and at the same time ensure nobody will ever use it. I will miss it”.
568 https://sphinxcontrib-hdl-diagrams.readthedocs.io/en/latest/examples/comb-full-adder.html
569 https://sphinxcontrib-hdl-diagrams.readthedocs.io/en/latest/examples/carry4.html
570 FuseSoC is used by MicroWatt and Western Digital cores
571 OpenTitan also uses FuseSoC
573 https://antmicro.com/blog/2020/12/ibex-support-in-verilator-yosys-via-uhdm-surelog/
574 https://cirosantilli.com/x86-paging
575 https://stackoverflow.com/questions/18431261/how-does-x86-paging-work
576 http://denninginstitute.com/modules/vm/red/i486page.html