1 # Resources and Specifications
3 This page aims to collect all the resources and specifications we need
4 in one place for quick access. We will try our best to keep links here
5 up-to-date. Feel free to add more links here.
11 * <https://openpowerfoundation.org/?resource_lib=power-isa-version-3-0>
12 * <https://openpowerfoundation.org/?resource_lib=ibm-power-isa-version-2-07-b>
14 # RISC-V Instruction Set Architecture
16 **PLEASE UPDATE** - we are no longer implementing full RISCV, only user-space
19 The Libre RISC-V Project is building a hybrid CPU/GPU SoC. As the name
20 of the project implies, we will be following the RISC-V ISA I due to it
21 being open-source and also because of the huge software and hardware
22 ecosystem building around it. There are other open-source ISAs but none
23 of them have the same momentum and energy behind it as RISC-V.
25 To fully take advantage of the RISC-V ecosystem, it is important to be
26 compliant with the RISC-V standards. Doing so will allow us to to reuse
27 most software as-is and avoid major forks.
29 * Official compiled PDFs of RISC-V ISA Manual:
30 <https://github.com/riscv/riscv-isa-manual/releases/latest>
31 * Working draft of the proposed RISC-V Bitmanipulation extension:
32 <https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-draft.pdf>
33 * RISC-V "V" Vector Extension:
34 <https://riscv.github.io/documents/riscv-v-spec/>
36 Note: As far as I know, we aren't using the RISC-V V Extension directly
37 at the moment. However, there are many wiki pages that make a reference
38 to the V extension so it would be good to include it here as a reference
39 for comparative/informative purposes with regard to Simple-V.
41 # IEEE Standard for Floating-Point Arithmetic (IEEE 754)
43 Almost all modern computers follow the IEEE Floating-Point Standard. Of
44 course, we will follow it as well for interoperability.
46 * IEEE 754-2019: <https://standards.ieee.org/standard/754-2019.html>
48 Note: Even though this is such an important standard used by everyone,
49 it is unfortunately not freely available and requires a payment to
50 access. However, each of the Libre RISC-V members already have access
55 The Khronos Group creates open standards for authoring and acceleration
56 of graphics, media, and computation. It is a requirement for our hybrid
57 CPU/GPU to be compliant with these standards *as well* as with IEEE754,
58 in order to be commercially-competitive in both areas: especially Vulkan
59 and OpenCL being the most important. SPIR-V is also important for the
62 Thus the [[zfpacc_proposal]] has been created which permits runtime dynamic
63 switching between different accuracy levels, in userspace applications.
65 **SPIR-V Main Page <https://www.khronos.org/registry/spir-v/>**
67 * SPIR-V 1.5 Specification Revision 1:
68 <https://www.khronos.org/registry/spir-v/specs/unified1/SPIRV.html>
69 * SPIR-V OpenCL Extended Instruction Set:
70 <https://www.khronos.org/registry/spir-v/specs/unified1/OpenCL.ExtendedInstructionSet.100.html>
71 * SPIR-V GLSL Extended Instruction Set:
72 <https://www.khronos.org/registry/spir-v/specs/unified1/GLSL.std.450.html>
74 **Vulkan Main Page <https://www.khronos.org/registry/vulkan/>**
77 <https://www.khronos.org/registry/vulkan/specs/1.1-extensions/html/index.html>
79 **OpenCL Main Page <https://www.khronos.org/registry/OpenCL/>**
81 * OpenCL 2.2 API Specification:
82 <https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_API.html>
83 * OpenCL 2.2 Extension Specification:
84 <https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_Ext.html>
85 * OpenCL 2.2 SPIR-V Environment Specification:
86 <https://www.khronos.org/registry/OpenCL/specs/2.2/html/OpenCL_Env.html>
88 Note: We are implementing hardware accelerated Vulkan and
89 OpenCL while relying on other software projects to translate APIs to
90 Vulkan. E.g. Zink allows for OpenGL-to-Vulkan in software.
92 # Graphics and Compute API Stack
94 I found this informative post that mentions Kazan and a whole bunch of
95 other stuff. It looks like *many* APIs can be emulated on top of Vulkan,
96 although performance is not evaluated.
98 <https://synappsis.wordpress.com/2017/06/03/opengl-over-vulkan-dev/>
100 # Various POWER Communities
101 - [An effort to make a 100% Libre POWER Laptop](https://www.powerpc-notebook.org/en/)
102 I still can't figure out if this chip is POWER8 or POWER9. Please verify!
103 - [Power Progress Community](https://www.powerprogress.org/campaigns/donations-to-all-the-power-progress-community-projects/]
104 Supporting/Raising awareness of various POWER related open projects on the FOSS
106 - [OpenPOWER](https://openpowerfoundation.org)
107 Promotes and ensure compliance with the Power ISA amongst members.
108 - [OpenCapi](https://opencapi.org)
109 High performance interconnect for POWER machines. One of the big advantages
110 of the POWER architecture. Notably more performant than PCIE Gen4, and is
111 designed to be layered on top of the physical PCIE link.
113 # Free Silicon Conference
115 The conference brought together experts and enthusiasts who want to build
116 a complete Free and Open Source CAD ecosystem for designing analog and
117 digital integrated circuits. The conference covered the full spectrum of
118 the design process, from system architecture, to layout and verification.
120 * <https://wiki.f-si.org/index.php/FSiC2019#Foundries.2C_PDKs_and_cell_libraries>
122 * LIP6's Coriolis - a set of backend design tools:
123 <https://www-soc.lip6.fr/equipe-cian/logiciels/coriolis/>
125 Note: The rest of LIP6's website is in French, but there is a UK flag
126 in the corner that gives the English version.
128 * KLayout - Layout viewer and editor: <https://www.klayout.de/>
130 # The OpenROAD Project
132 OpenROAD seeks to develop and foster an autonomous, 24-hour, open-source
133 layout generation flow (RTL-to-GDS).
135 * <https://theopenroadproject.org/>
137 # Other RISC-V GPU attempts
139 * <https://fossi-foundation.org/2019/09/03/gsoc-64b-pointers-in-rv32>
141 * <http://bjump.org/manycore/>
143 * <https://resharma.github.io/RISCV32-GPU/>
145 TODO: Get in touch and discuss collaboration
147 # Tests, Benchmarks, Conformance, Compliance, Verification, etc.
151 RISC-V Foundation is in the process of creating an official conformance
152 test. It's still in development as far as I can tell.
154 * //TODO LINK TO RISC-V CONFORMANCE TEST
158 IEEE 754 has no official tests for floating-point but there are several
159 well-known third party tools to check such as John Hauser's SoftFloat
162 * <http://www.jhauser.us/arithmetic/>
164 Jacob is also making a Rust library to check IEEE 754 operations.
166 * <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-September/002737.html>
168 A cool paper I came across in my research is "IeeeCC754++ : An Advanced
169 Set of Tools to Check IEEE 754-2008 Conformity" by Dr. Matthias Hüsken.
171 * Direct link to PDF:
172 <http://elpub.bib.uni-wuppertal.de/servlets/DerivateServlet/Derivate-7505/dc1735.pdf>
176 OpenCL Conformance Tests
178 * <https://github.com/KhronosGroup/OpenCL-CTS>
180 Vulkan Conformance Tests
182 * <https://github.com/KhronosGroup/VK-GL-CTS>
184 MAJOR NOTE: We are **not** allowed to say we are compliant with any of
185 the Khronos standards until we actually make an official submission,
186 do the paperwork, and pay the relevant fees.
188 ## Formal Verification
190 Formal verification of Libre RISC-V ensures that it is bug-free in
191 regards to what we specify. Of course, it is important to do the formal
192 verification as a final step in the development process before we produce
193 thousands or millions of silicon.
195 Some learning resources I found in the community:
197 * ZipCPU: <http://zipcpu.com/>
199 ZipCPU provides a comprehensive tutorial for beginners and many exercises/quizzes/slides: <http://zipcpu.com/tutorial/>
202 * Western Digital's SweRV CPU blog (I recommend looking at all their posts): <https://tomverbeure.github.io/>
204 <https://tomverbeure.github.io/risc-v/2018/11/19/A-Bug-Free-RISC-V-Core-without-Simulation.html>
206 <https://tomverbeure.github.io/rtl/2019/01/04/Under-the-Hood-of-Formal-Verification.html>
210 * <https://www.ohwr.org/project/wishbone-gen>
214 ## Adding new instructions:
216 * <https://archive.fosdem.org/2015/schedule/event/llvm_internal_asm/>
220 * <https://danluu.com/branch-prediction/>
223 # Information Resources and Tutorials
225 This section is primarily a series of useful links found online
227 * FSiC2019 <https://wiki.f-si.org/index.php/FSiC2019>
228 * Fundamentals to learn to get started [[3d_gpu/tutorial]]
229 * <https://github.com/timvideos/litex-buildenv/wiki/LiteX-for-Hardware-Engineers>
230 * <https://jeffrey.co.in/blog/2014/01/d-flip-flop-using-migen/>
231 * <http://lists.libre-riscv.org/pipermail/libre-riscv-dev/2019-March/000705.html>
232 * <https://chisel.eecs.berkeley.edu/api/latest/chisel3/util/DecoupledIO.html>
233 * <http://www.clifford.at/papers/2016/yosys-synth-formal/slides.pdf>
234 * <http://blog.lambdaconcept.com/doku.php?id=migen:tutorial>
235 * Samuel's KC5 code <http://chiselapp.com/user/kc5tja/repository/kestrel-3/dir?ci=6c559135a301f321&name=cores/cpu>
236 * <https://chips4makers.io/blog/>
237 * <https://hackaday.io/project/7817-zynqberry>
238 * <https://wiki.f-si.org/index.php/FSiC2019>
239 * <https://github.com/efabless/raven-picorv32> - <https://efabless.com>
240 * <https://efabless.com/design_catalog/default>
241 * <https://toyota-ai.ventures/>
242 * <https://github.com/lambdaconcept/minerva>
243 * <https://en.wikipedia.org/wiki/Liskov_substitution_principle>
244 * <https://en.wikipedia.org/wiki/Principle_of_least_astonishment>
245 * <https://peertube.f-si.org/videos/watch/379ef007-40b7-4a51-ba1a-0db4f48e8b16>
246 * <https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.md>
247 * <https://mshahrad.github.io/openpiton-asplos16.html>
248 * <https://wiki.f-si.org/index.php/The_Raven_chip:_First-time_silicon_success_with_qflow_and_efabless>
249 * <http://smallcultfollowing.com/babysteps/blog/2019/04/19/aic-adventures-in-consensus/>
250 * <http://www.crnhq.org/12-Skills-Summary.aspx?rw=c>
251 * <http://bugs.libre-riscv.org/buglist.cgi?columnlist=assigned_to%2Cbug_status%2Cresolution%2Cshort_desc%2Ccf_budget&f1=cf_nlnet_milestone&o1=equals&query_format=advanced&resolution=---&v1=NLnet.2019.02>
252 * <https://pdfs.semanticscholar.org/5060/4e9aff0e37089c4ab9a376c3f35761ffe28b.pdf>
253 * <http://www.acsel-lab.com/arithmetic/arith15/papers/ARITH15_Takagi.pdf>
254 * <https://youtu.be/o5Ihqg72T3c>
255 * <http://flopoco.gforge.inria.fr/>
256 * Fundamentals of Modern VLSI Devices <https://groups.google.com/a/groups.riscv.org/d/msg/hw-dev/b4pPvlzBzu0/7hDfxArEAgAJ>
260 * <https://github.com/Isotel/mixedsim>
261 * <http://www.vlsiacademy.org/open-source-cad-tools.html>
262 * <http://ngspice.sourceforge.net/adms.html>
263 * <https://en.wikipedia.org/wiki/Verilog-AMS#Open_Source_Implementations>
265 # Libre-RISC-V Standards
267 This list auto-generated from a page tag "standards":
269 [[!inline pages="tagged(standards)" actions="no" archive="yes" quick="yes"]]
273 [[resources/server-setup/git-mirroring]]