riscv/decode.h

   1 #ifndef _RISCV_DECODE_H
   2 #define _RISCV_DECODE_H
   3
   4 #define __STDC_LIMIT_MACROS
   5 #include <stdint.h>
   6 typedef int int128_t __attribute__((mode(TI)));
   7 typedef unsigned int uint128_t __attribute__((mode(TI)));
   8
   9 #define support_64bit 1
  10 typedef int64_t sreg_t;
  11 typedef uint64_t reg_t;
  12 typedef uint64_t freg_t;
  13
  14 const int OPCODE_BITS = 7;
  15 const int JTYPE_OPCODE_BITS = 5;
  16
  17 const int GPR_BITS = 8*sizeof(reg_t);
  18 const int GPRID_BITS = 5;
  19 const int NGPR = 1 << GPRID_BITS;
  20
  21 const int FPR_BITS = 64;
  22 const int FPRID_BITS = 5;
  23 const int NFPR = 1 << FPRID_BITS;
  24
  25 const int IMM_BITS = 12;
  26 const int TARGET_BITS = 27;
  27 const int SHAMT_BITS = 6;
  28 const int FUNCT_BITS = 3;
  29 const int FUNCTR_BITS = 7;
  30 const int FFUNCT_BITS = 5;
  31 const int BIGIMM_BITS = 20;
  32 const int BRANCH_ALIGN_BITS = 1;
  33 const int JUMP_ALIGN_BITS = 1;
  34
  35 #define SR_ET    0x0000000000000001ULL
  36 #define SR_PS    0x0000000000000004ULL
  37 #define SR_S     0x0000000000000008ULL
  38 #define SR_EF    0x0000000000000010ULL
  39 #define SR_UX    0x0000000000000020ULL
  40 #define SR_SX    0x0000000000000040ULL
  41 #define SR_IM    0x000000000000FF00ULL
  42 #define SR_ZERO  ~(SR_ET | SR_PS | SR_S | SR_EF | SR_UX | SR_SX | SR_IM)
  43 #define SR_IM_SHIFT 8
  44 #define TIMER_IRQ 7
  45
  46 #define FP_RD_NE  0
  47 #define FP_RD_0   1
  48 #define FP_RD_DN  2
  49 #define FP_RD_UP  3
  50 #define FSR_RD_SHIFT 5
  51 #define FSR_RD   (0x3 << FSR_RD_SHIFT)
  52
  53 #define FPEXC_NX 0x01
  54 #define FPEXC_UF 0x02
  55 #define FPEXC_OF 0x04
  56 #define FPEXC_DZ 0x02
  57 #define FPEXC_NV 0x10
  58
  59 #define FSR_AEXC_SHIFT 0
  60 #define FSR_NVA  (FPEXC_NV << FSR_AEXC_SHIFT)
  61 #define FSR_OFA  (FPEXC_OF << FSR_AEXC_SHIFT)
  62 #define FSR_UFA  (FPEXC_UF << FSR_AEXC_SHIFT)
  63 #define FSR_DZA  (FPEXC_DZ << FSR_AEXC_SHIFT)
  64 #define FSR_NXA  (FPEXC_NX << FSR_AEXC_SHIFT)
  65 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
  66
  67 #define FSR_ZERO ~(FSR_RD | FSR_AEXC)
  68
  69 // note: bit fields are in little-endian order
  70 struct itype_t
  71 {
  72   signed imm12 : IMM_BITS;
  73   unsigned funct : FUNCT_BITS;
  74   unsigned rs1 : GPRID_BITS;
  75   unsigned rdi : GPRID_BITS;
  76   unsigned opcode : OPCODE_BITS;
  77 };
  78
  79 struct jtype_t
  80 {
  81   unsigned target : TARGET_BITS;
  82   unsigned jump_opcode : JTYPE_OPCODE_BITS;
  83 };
  84
  85 struct rtype_t
  86 {
  87   unsigned rdr : GPRID_BITS;
  88   unsigned functr : FUNCTR_BITS;
  89   unsigned funct : FUNCT_BITS;
  90   unsigned rs1 : GPRID_BITS;
  91   unsigned rs2 : GPRID_BITS;
  92   unsigned opcode : OPCODE_BITS;
  93 };
  94
  95 struct btype_t
  96 {
  97   unsigned bigimm : BIGIMM_BITS;
  98   unsigned rdi : GPRID_BITS;
  99   unsigned opcode : OPCODE_BITS;
 100 };
 101
 102 struct ftype_t
 103 {
 104   unsigned rdr : FPRID_BITS;
 105   unsigned rs3 : FPRID_BITS;
 106   unsigned ffunct : FFUNCT_BITS;
 107   unsigned rs1 : FPRID_BITS;
 108   unsigned rs2 : FPRID_BITS;
 109   unsigned opcode : OPCODE_BITS;
 110 };
 111
 112 union insn_t
 113 {
 114   itype_t itype;
 115   jtype_t jtype;
 116   rtype_t rtype;
 117   btype_t btype;
 118   ftype_t ftype;
 119   uint32_t bits;
 120 };
 121
 122 #if 0
 123 #include <stdio.h>
 124 class trace_writeback
 125 {
 126 public:
 127   trace_writeback(reg_t* _rf, int _rd) : rf(_rf), rd(_rd) {}
 128
 129   reg_t operator = (reg_t rhs)
 130   {
 131     printf("R[%x] <= %llx\n",rd,(long long)rhs);
 132     rf[rd] = rhs;
 133     return rhs;
 134   }
 135
 136 private:
 137   reg_t* rf;
 138   int rd;
 139 };
 140
 141 #define do_writeback(rf,rd) trace_writeback(rf,rd)
 142 #else
 143 #define do_writeback(rf,rd) rf[rd]
 144 #endif
 145
 146 // helpful macros, etc
 147 #define RS1 R[insn.rtype.rs1]
 148 #define RS2 R[insn.rtype.rs2]
 149 #define RDR do_writeback(R,insn.rtype.rdr)
 150 #define RDI do_writeback(R,insn.itype.rdi)
 151 #define FRS1 FR[insn.ftype.rs1]
 152 #define FRS2 FR[insn.ftype.rs2]
 153 #define FRS3 FR[insn.ftype.rs3]
 154 #define FRDR FR[insn.ftype.rdr]
 155 #define FRDI FR[insn.itype.rdi]
 156 #define BIGIMM insn.btype.bigimm
 157 #define SIMM insn.itype.imm12
 158 #define SHAMT (insn.itype.imm12 & 0x3F)
 159 #define SHAMTW (insn.itype.imm12 & 0x1F)
 160 #define TARGET insn.jtype.target
 161 #define BRANCH_TARGET (npc + (SIMM << BRANCH_ALIGN_BITS))
 162 #define JUMP_TARGET ((npc & ~((1<<(TARGET_BITS+JUMP_ALIGN_BITS))-1)) + (TARGET << JUMP_ALIGN_BITS))
 163
 164 #define require_supervisor if(!(sr & SR_S)) throw trap_privileged_instruction
 165 #define require64 if(gprlen != 64) throw trap_illegal_instruction
 166 #define require_fp if(!(sr & SR_EF)) throw trap_fp_disabled
 167 #define cmp_trunc(reg) (reg_t(reg) << (64-gprlen))
 168 #define set_fp_exceptions ({ set_fsr(fsr | \
 169                                (softfloat_exceptionFlags << FSR_AEXC_SHIFT)); \
 170                              softfloat_exceptionFlags = 0; })
 171
 172 static inline sreg_t sext32(int32_t arg)
 173 {
 174   return arg;
 175 }
 176
 177 #endif