riscv/decode.h

   1 #ifndef _RISCV_DECODE_H
   2 #define _RISCV_DECODE_H
   3
   4 #define __STDC_LIMIT_MACROS
   5 #include <stdint.h>
   6 typedef int int128_t __attribute__((mode(TI)));
   7 typedef unsigned int uint128_t __attribute__((mode(TI)));
   8
   9 #define support_64bit 1
  10 typedef int64_t sreg_t;
  11 typedef uint64_t reg_t;
  12 typedef uint64_t freg_t;
  13
  14 const int OPCODE_BITS = 7;
  15 const int JTYPE_OPCODE_BITS = 5;
  16
  17 const int GPR_BITS = 8*sizeof(reg_t);
  18 const int GPRID_BITS = 5;
  19 const int NGPR = 1 << GPRID_BITS;
  20
  21 const int FPR_BITS = 64;
  22 const int FPRID_BITS = 5;
  23 const int NFPR = 1 << FPRID_BITS;
  24
  25 const int IMM_BITS = 12;
  26 const int TARGET_BITS = 27;
  27 const int SHAMT_BITS = 6;
  28 const int FUNCT_BITS = 3;
  29 const int FUNCTR_BITS = 7;
  30 const int FFUNCT_BITS = 5;
  31 const int BIGIMM_BITS = 20;
  32 const int BRANCH_ALIGN_BITS = 1;
  33 const int JUMP_ALIGN_BITS = 1;
  34
  35 #define SR_ET    0x0000000000000001ULL
  36 #define SR_PS    0x0000000000000004ULL
  37 #define SR_S     0x0000000000000008ULL
  38 #define SR_EF    0x0000000000000010ULL
  39 #define SR_UX    0x0000000000000020ULL
  40 #define SR_SX    0x0000000000000040ULL
  41 #define SR_IM    0x000000000000FF00ULL
  42 #define SR_ZERO  ~(SR_ET | SR_PS | SR_S | SR_EF | SR_UX | SR_SX | SR_IM)
  43 #define SR_IM_SHIFT 8
  44 #define TIMER_IRQ 7
  45
  46 #define FP_RD_NE  0
  47 #define FP_RD_0   1
  48 #define FP_RD_DN  2
  49 #define FP_RD_UP  3
  50 #define FP_RD_NMM 4
  51 #define FSR_RD_SHIFT 10
  52 #define FSR_RD   (0x7 << FSR_RD_SHIFT)
  53
  54 #define FPEXC_NX 0x01
  55 #define FPEXC_UF 0x02
  56 #define FPEXC_OF 0x04
  57 #define FPEXC_DZ 0x02
  58 #define FPEXC_NV 0x10
  59
  60 #define FSR_CEXC_SHIFT 5
  61 #define FSR_NVC  (FPEXC_NV << FSR_CEXC_SHIFT)
  62 #define FSR_OFC  (FPEXC_OF << FSR_CEXC_SHIFT)
  63 #define FSR_UFC  (FPEXC_UF << FSR_CEXC_SHIFT)
  64 #define FSR_DZC  (FPEXC_DZ << FSR_CEXC_SHIFT)
  65 #define FSR_NXC  (FPEXC_NX << FSR_CEXC_SHIFT)
  66 #define FSR_CEXC (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
  67
  68 #define FSR_AEXC_SHIFT 0
  69 #define FSR_NVA  (FPEXC_NV << FSR_AEXC_SHIFT)
  70 #define FSR_OFA  (FPEXC_OF << FSR_AEXC_SHIFT)
  71 #define FSR_UFA  (FPEXC_UF << FSR_AEXC_SHIFT)
  72 #define FSR_DZA  (FPEXC_DZ << FSR_AEXC_SHIFT)
  73 #define FSR_NXA  (FPEXC_NX << FSR_AEXC_SHIFT)
  74 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
  75
  76 #define FSR_ZERO ~(FSR_RD | FSR_AEXC | FSR_CEXC)
  77
  78 // note: bit fields are in little-endian order
  79 struct itype_t
  80 {
  81   unsigned imm : IMM_BITS;
  82   unsigned funct : FUNCT_BITS;
  83   unsigned rb : GPRID_BITS;
  84   unsigned ra : GPRID_BITS;
  85   unsigned opcode : OPCODE_BITS;
  86 };
  87
  88 struct jtype_t
  89 {
  90   unsigned target : TARGET_BITS;
  91   unsigned jump_opcode : JTYPE_OPCODE_BITS;
  92 };
  93
  94 struct rtype_t
  95 {
  96   unsigned rc : GPRID_BITS;
  97   unsigned functr : FUNCTR_BITS;
  98   unsigned funct : FUNCT_BITS;
  99   unsigned rb : GPRID_BITS;
 100   unsigned ra : GPRID_BITS;
 101   unsigned opcode : OPCODE_BITS;
 102 };
 103
 104 struct btype_t
 105 {
 106   unsigned bigimm : BIGIMM_BITS;
 107   unsigned rt : GPRID_BITS;
 108   unsigned opcode : OPCODE_BITS;
 109 };
 110
 111 struct ftype_t
 112 {
 113   unsigned rc : FPRID_BITS;
 114   unsigned rd : FPRID_BITS;
 115   unsigned ffunct : FFUNCT_BITS;
 116   unsigned rb : FPRID_BITS;
 117   unsigned ra : FPRID_BITS;
 118   unsigned opcode : OPCODE_BITS;
 119 };
 120
 121 union insn_t
 122 {
 123   itype_t itype;
 124   jtype_t jtype;
 125   rtype_t rtype;
 126   btype_t btype;
 127   ftype_t ftype;
 128   uint32_t bits;
 129 };
 130
 131 // helpful macros, etc
 132 #define RA R[insn.rtype.ra]
 133 #define RB R[insn.rtype.rb]
 134 #define RC R[insn.rtype.rc]
 135 #define FRA FR[insn.ftype.ra]
 136 #define FRB FR[insn.ftype.rb]
 137 #define FRC FR[insn.ftype.rc]
 138 #define FRD FR[insn.ftype.rd]
 139 #define BIGIMM insn.btype.bigimm
 140 #define IMM insn.itype.imm
 141 #define SIMM ((int32_t)((uint32_t)insn.itype.imm<<(32-IMM_BITS))>>(32-IMM_BITS))
 142 #define SHAMT (insn.itype.imm & 0x3F)
 143 #define SHAMTW (insn.itype.imm & 0x1F)
 144 #define TARGET insn.jtype.target
 145 #define BRANCH_TARGET (npc + (SIMM << BRANCH_ALIGN_BITS))
 146 #define JUMP_TARGET ((npc & ~((1<<(TARGET_BITS+JUMP_ALIGN_BITS))-1)) + (TARGET << JUMP_ALIGN_BITS))
 147
 148 #define require_supervisor if(!(sr & SR_S)) throw trap_privileged_instruction
 149 #define require64 if(gprlen != 64) throw trap_illegal_instruction
 150 #define require_fp if(!(sr & SR_EF)) throw trap_fp_disabled
 151 #define cmp_trunc(reg) (reg_t(reg) << (64-gprlen))
 152 #define set_fp_exceptions ({ set_fsr((fsr & ~FSR_CEXC) | \
 153                                 (softfloat_exceptionFlags << FSR_AEXC_SHIFT) | \
 154                                 (softfloat_exceptionFlags << FSR_CEXC_SHIFT)); \
 155                              softfloat_exceptionFlags = 0; })
 156
 157 static inline sreg_t sext32(int32_t arg)
 158 {
 159   return arg;
 160 }
 161
 162 #endif