riscv/decode.h

   1 #ifndef _RISCV_DECODE_H
   2 #define _RISCV_DECODE_H
   3
   4 #define __STDC_LIMIT_MACROS
   5 #include <stdint.h>
   6 typedef int int128_t __attribute__((mode(TI)));
   7 typedef unsigned int uint128_t __attribute__((mode(TI)));
   8
   9 #define support_64bit 1
  10 typedef int64_t sreg_t;
  11 typedef uint64_t reg_t;
  12
  13 union freg_t
  14 {
  15   float sp;
  16   double dp;
  17   uint64_t bits;
  18 };
  19
  20 const int OPCODE_BITS = 7;
  21 const int JTYPE_OPCODE_BITS = 5;
  22
  23 const int GPR_BITS = 8*sizeof(reg_t);
  24 const int GPRID_BITS = 5;
  25 const int NGPR = 1 << GPRID_BITS;
  26
  27 const int FPR_BITS = 64;
  28 const int FPRID_BITS = 5;
  29 const int NFPR = 1 << FPRID_BITS;
  30
  31 const int IMM_BITS = 12;
  32 const int TARGET_BITS = 27;
  33 const int SHAMT_BITS = 6;
  34 const int FUNCT_BITS = 3;
  35 const int FFUNCT_BITS = 5;
  36 const int BIGIMM_BITS = 20;
  37
  38 #define SR_ET    0x0000000000000001ULL
  39 #define SR_PS    0x0000000000000004ULL
  40 #define SR_S     0x0000000000000008ULL
  41 #define SR_EF    0x0000000000000010ULL
  42 #define SR_UX    0x0000000000000020ULL
  43 #define SR_KX    0x0000000000000040ULL
  44 #define SR_IM    0x000000000000FF00ULL
  45 #define SR_ZERO  0xFFFFFFFFFFFF0082ULL
  46
  47 // note: bit fields are in little-endian order
  48 struct itype_t
  49 {
  50   unsigned imm : IMM_BITS;
  51   unsigned funct : FUNCT_BITS;
  52   unsigned rb : GPRID_BITS;
  53   unsigned ra : GPRID_BITS;
  54   unsigned opcode : OPCODE_BITS;
  55 };
  56
  57 struct jtype_t
  58 {
  59   unsigned target : TARGET_BITS;
  60   unsigned jump_opcode : JTYPE_OPCODE_BITS;
  61 };
  62
  63 struct rtype_t
  64 {
  65   unsigned rc : GPRID_BITS;
  66   unsigned shamt : SHAMT_BITS;
  67   unsigned unused : 1;
  68   unsigned funct : FUNCT_BITS;
  69   unsigned rb : GPRID_BITS;
  70   unsigned ra : GPRID_BITS;
  71   unsigned opcode : OPCODE_BITS;
  72 };
  73
  74 struct btype_t
  75 {
  76   unsigned bigimm : BIGIMM_BITS;
  77   unsigned rt : GPRID_BITS;
  78   unsigned opcode : OPCODE_BITS;
  79 };
  80
  81 struct ftype_t
  82 {
  83   unsigned rc : FPRID_BITS;
  84   unsigned rd : FPRID_BITS;
  85   unsigned ffunct : FFUNCT_BITS;
  86   unsigned rb : FPRID_BITS;
  87   unsigned ra : FPRID_BITS;
  88   unsigned opcode : OPCODE_BITS;
  89 };
  90
  91 union insn_t
  92 {
  93   itype_t itype;
  94   jtype_t jtype;
  95   rtype_t rtype;
  96   btype_t btype;
  97   ftype_t ftype;
  98   uint32_t bits;
  99 };
 100
 101 // helpful macros, etc
 102 #define RA R[insn.rtype.ra]
 103 #define RB R[insn.rtype.rb]
 104 #define RC R[insn.rtype.rc]
 105 #define FRA FR[insn.ftype.ra]
 106 #define FRB FR[insn.ftype.rb]
 107 #define FRC FR[insn.ftype.rc]
 108 #define FRD FR[insn.ftype.rd]
 109 #define BIGIMM insn.btype.bigimm
 110 #define IMM insn.itype.imm
 111 #define SIMM ((int32_t)((uint32_t)insn.itype.imm<<(32-IMM_BITS))>>(32-IMM_BITS))
 112 #define SHAMT insn.rtype.shamt
 113 #define TARGET insn.jtype.target
 114 #define BRANCH_TARGET (npc + (SIMM*sizeof(insn_t)))
 115 #define JUMP_TARGET ((npc & ~((1<<TARGET_BITS)*sizeof(insn_t)-1)) + TARGET*sizeof(insn_t))
 116
 117 #define require_supervisor if(!(sr & SR_S)) throw trap_privileged_instruction
 118 #define require64 if(gprlen != 64) throw trap_illegal_instruction
 119 #define require_fp if(!(sr & SR_EF)) throw trap_fp_disabled
 120 #define cmp_trunc(reg) (reg_t(reg) << (64-gprlen))
 121
 122 static inline sreg_t sext32(int32_t arg)
 123 {
 124   return arg;
 125 }
 126
 127 #endif