riscv/execute.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "mmu.h"
   5 #include <cassert>
   6
   7
   8 static void commit_log_stash_privilege(state_t* state)
   9 {
  10 #ifdef RISCV_ENABLE_COMMITLOG
  11   state->last_inst_priv = state->prv;
  12 #endif
  13 }
  14
  15 static void commit_log_print_insn(state_t* state, reg_t pc, insn_t insn)
  16 {
  17 #ifdef RISCV_ENABLE_COMMITLOG
  18   int32_t priv = state->last_inst_priv;
  19   uint64_t mask = (insn.length() == 8 ? uint64_t(0) : (uint64_t(1) << (insn.length() * 8))) - 1;
  20   if (state->log_reg_write.addr) {
  21     fprintf(stderr, "%1d 0x%016" PRIx64 " (0x%08" PRIx64 ") %c%2" PRIu64 " 0x%016" PRIx64 "\n",
  22             priv,
  23             pc,
  24             insn.bits() & mask,
  25             state->log_reg_write.addr & 1 ? 'f' : 'x',
  26             state->log_reg_write.addr >> 1,
  27             state->log_reg_write.data);
  28   } else {
  29     fprintf(stderr, "%1d 0x%016" PRIx64 " (0x%08" PRIx64 ")\n", priv, pc, insn.bits() & mask);
  30   }
  31   state->log_reg_write.addr = 0;
  32 #endif
  33 }
  34
  35 inline void processor_t::update_histogram(reg_t pc)
  36 {
  37 #ifdef RISCV_ENABLE_HISTOGRAM
  38   pc_histogram[pc]++;
  39 #endif
  40 }
  41
  42 static reg_t execute_insn(processor_t* p, reg_t pc, insn_fetch_t fetch)
  43 {
  44   commit_log_stash_privilege(p->get_state());
  45   reg_t npc = fetch.func(p, fetch.insn, pc);
  46   if (!invalid_pc(npc)) {
  47     commit_log_print_insn(p->get_state(), pc, fetch.insn);
  48     p->update_histogram(pc);
  49   }
  50   return npc;
  51 }
  52
  53 // fetch/decode/execute loop
  54 void processor_t::step(size_t n)
  55 {
  56   if (state.dcsr.debugint && state.dcsr.cause == DCSR_CAUSE_NONE) {
  57     enter_debug_mode(DCSR_CAUSE_DEBUGINT);
  58   }
  59
  60   while (n > 0) {
  61     size_t instret = 0;
  62     reg_t pc = state.pc;
  63     mmu_t* _mmu = mmu;
  64
  65     #define advance_pc() \
  66      if (unlikely(invalid_pc(pc))) { \
  67        switch (pc) { \
  68          case PC_SERIALIZE_BEFORE: state.serialized = true; break; \
  69          case PC_SERIALIZE_AFTER: instret++; break; \
  70          default: abort(); \
  71        } \
  72        pc = state.pc; \
  73        break; \
  74      } else { \
  75        state.pc = pc; \
  76        instret++; \
  77      }
  78
  79     try
  80     {
  81       take_interrupt();
  82
  83       if (unlikely(debug))
  84       {
  85         while (instret < n)
  86         {
  87           insn_fetch_t fetch = mmu->load_insn(pc);
  88           if (!state.serialized)
  89             disasm(fetch.insn);
  90           pc = execute_insn(this, pc, fetch);
  91           advance_pc();
  92         }
  93       }
  94       else while (instret < n)
  95       {
  96         size_t idx = _mmu->icache_index(pc);
  97         auto ic_entry = _mmu->access_icache(pc);
  98
  99         #define ICACHE_ACCESS(i) { \
 100           insn_fetch_t fetch = ic_entry->data; \
 101           ic_entry++; \
 102           pc = execute_insn(this, pc, fetch); \
 103           if (i == mmu_t::ICACHE_ENTRIES-1) break; \
 104           if (unlikely(ic_entry->tag != pc)) goto miss; \
 105           if (unlikely(instret+1 == n)) break; \
 106           instret++; \
 107           state.pc = pc; \
 108         }
 109
 110         switch (idx) {
 111           #include "icache.h"
 112         }
 113
 114         advance_pc();
 115         continue;
 116
 117 miss:
 118         advance_pc();
 119         // refill I$ if it looks like there wasn't a taken branch
 120         if (pc > (ic_entry-1)->tag && pc <= (ic_entry-1)->tag + MAX_INSN_LENGTH)
 121           _mmu->refill_icache(pc, ic_entry);
 122       }
 123     }
 124     catch(trap_t& t)
 125     {
 126       take_trap(t, pc);
 127       n = instret;
 128     }
 129
 130     state.minstret += instret;
 131     n -= instret;
 132   }
 133 }