riscv/execute.cc

   1 // See LICENSE for license details.
   2
   3 #include "processor.h"
   4 #include "mmu.h"
   5 #include <cassert>
   6
   7
   8 static void commit_log_stash_privilege(state_t* state)
   9 {
  10 #ifdef RISCV_ENABLE_COMMITLOG
  11   state->last_inst_priv = get_field(state->mstatus, MSTATUS_PRV);
  12 #endif
  13 }
  14
  15 static void commit_log_print_insn(state_t* state, reg_t pc, insn_t insn)
  16 {
  17 #ifdef RISCV_ENABLE_COMMITLOG
  18   int32_t priv = state->last_inst_priv;
  19   uint64_t mask = (insn.length() == 8 ? uint64_t(0) : (uint64_t(1) << (insn.length() * 8))) - 1;
  20   if (state->log_reg_write.addr) {
  21     fprintf(stderr, "%1d 0x%016" PRIx64 " (0x%08" PRIx64 ") %c%2" PRIu64 " 0x%016" PRIx64 "\n",
  22             priv,
  23             pc,
  24             insn.bits() & mask,
  25             state->log_reg_write.addr & 1 ? 'f' : 'x',
  26             state->log_reg_write.addr >> 1,
  27             state->log_reg_write.data);
  28   } else {
  29     fprintf(stderr, "%1d 0x%016" PRIx64 " (0x%08" PRIx64 ")\n", priv, pc, insn.bits() & mask);
  30   }
  31   state->log_reg_write.addr = 0;
  32 #endif
  33 }
  34
  35 inline void processor_t::update_histogram(size_t pc)
  36 {
  37 #ifdef RISCV_ENABLE_HISTOGRAM
  38   size_t idx = pc >> 2;
  39   pc_histogram[idx]++;
  40 #endif
  41 }
  42
  43 static reg_t execute_insn(processor_t* p, reg_t pc, insn_fetch_t fetch)
  44 {
  45   commit_log_stash_privilege(p->get_state());
  46   reg_t npc = fetch.func(p, fetch.insn, pc);
  47   if (npc != PC_SERIALIZE) {
  48     commit_log_print_insn(p->get_state(), pc, fetch.insn);
  49     p->update_histogram(pc);
  50   }
  51   return npc;
  52 }
  53
  54 // fetch/decode/execute loop
  55 void processor_t::step(size_t n)
  56 {
  57   while (run && n > 0) {
  58     size_t instret = 0;
  59     reg_t pc = state.pc;
  60     mmu_t* _mmu = mmu;
  61
  62     #define advance_pc() \
  63      if (unlikely(pc == PC_SERIALIZE)) { \
  64        pc = state.pc; \
  65        state.serialized = true; \
  66        break; \
  67      } else { \
  68        state.pc = pc; \
  69        instret++; \
  70      }
  71
  72     try
  73     {
  74       check_timer();
  75       take_interrupt();
  76
  77       if (unlikely(debug))
  78       {
  79         while (instret < n)
  80         {
  81           insn_fetch_t fetch = mmu->load_insn(pc);
  82           if (!state.serialized)
  83             disasm(fetch.insn);
  84           pc = execute_insn(this, pc, fetch);
  85           advance_pc();
  86         }
  87       }
  88       else while (instret < n)
  89       {
  90         size_t idx = _mmu->icache_index(pc);
  91         auto ic_entry = _mmu->access_icache(pc);
  92
  93         #define ICACHE_ACCESS(i) { \
  94           insn_fetch_t fetch = ic_entry->data; \
  95           ic_entry++; \
  96           pc = execute_insn(this, pc, fetch); \
  97           if (i == mmu_t::ICACHE_ENTRIES-1) break; \
  98           if (unlikely(ic_entry->tag != pc)) goto miss; \
  99           if (unlikely(instret+1 == n)) break; \
 100           instret++; \
 101           state.pc = pc; \
 102         }
 103
 104         switch (idx) {
 105           #include "icache.h"
 106         }
 107
 108         advance_pc();
 109         continue;
 110
 111 miss:
 112         advance_pc();
 113         // refill I$ if it looks like there wasn't a taken branch
 114         if (pc > (ic_entry-1)->tag && pc <= (ic_entry-1)->tag + MAX_INSN_LENGTH)
 115           _mmu->refill_icache(pc, ic_entry);
 116       }
 117     }
 118     catch(trap_t& t)
 119     {
 120       take_trap(t, pc);
 121     }
 122
 123     state.minstret += instret;
 124     n -= instret;
 125   }
 126 }