riscv/execute.h

   1 /* Automatically generated by parse-opcodes */
   2 switch((insn.bits >> 0x0) & 0x7f)
   3 {
   4   case 0x0:
   5   {
   6     #include "insns/c_addi.h"
   7     break;
   8   }
   9   case 0x1:
  10   {
  11     #include "insns/c_li.h"
  12     break;
  13   }
  14   case 0x3:
  15   {
  16     switch((insn.bits >> 0x7) & 0x7)
  17     {
  18       case 0x0:
  19       {
  20         #include "insns/lb.h"
  21         break;
  22       }
  23       case 0x1:
  24       {
  25         #include "insns/lh.h"
  26         break;
  27       }
  28       case 0x2:
  29       {
  30         #include "insns/lw.h"
  31         break;
  32       }
  33       case 0x3:
  34       {
  35         #include "insns/ld.h"
  36         break;
  37       }
  38       case 0x4:
  39       {
  40         #include "insns/lbu.h"
  41         break;
  42       }
  43       case 0x5:
  44       {
  45         #include "insns/lhu.h"
  46         break;
  47       }
  48       case 0x6:
  49       {
  50         #include "insns/lwu.h"
  51         break;
  52       }
  53       default:
  54       {
  55         throw trap_illegal_instruction;
  56       }
  57     }
  58     break;
  59   }
  60   case 0x7:
  61   {
  62     switch((insn.bits >> 0x7) & 0x7)
  63     {
  64       case 0x2:
  65       {
  66         #include "insns/flw.h"
  67         break;
  68       }
  69       case 0x3:
  70       {
  71         #include "insns/fld.h"
  72         break;
  73       }
  74       default:
  75       {
  76         throw trap_illegal_instruction;
  77       }
  78     }
  79     break;
  80   }
  81   case 0xb:
  82   {
  83     switch((insn.bits >> 0x7) & 0x7)
  84     {
  85       case 0x0:
  86       {
  87         if((insn.bits & 0x1ffff) == 0x280b)
  88         {
  89           #include "insns/sbseg_v.h"
  90           break;
  91         }
  92         if((insn.bits & 0x1ffff) == 0x100b)
  93         {
  94           #include "insns/lbst_v.h"
  95           break;
  96         }
  97         if((insn.bits & 0x1ffff) == 0x180b)
  98         {
  99           #include "insns/sbst_v.h"
 100           break;
 101         }
 102         if((insn.bits & 0x3fffff) == 0xb)
 103         {
 104           #include "insns/lb_v.h"
 105           break;
 106         }
 107         if((insn.bits & 0x1ffff) == 0x200b)
 108         {
 109           #include "insns/lbseg_v.h"
 110           break;
 111         }
 112         if((insn.bits & 0x3fffff) == 0x1000b)
 113         {
 114           #include "insns/mov_vv.h"
 115           break;
 116         }
 117         if((insn.bits & 0x3fffff) == 0x1800b)
 118         {
 119           #include "insns/fmov_vv.h"
 120           break;
 121         }
 122         if((insn.bits & 0x3fffff) == 0x80b)
 123         {
 124           #include "insns/sb_v.h"
 125           break;
 126         }
 127         throw trap_illegal_instruction;
 128       }
 129       case 0x1:
 130       {
 131         if((insn.bits & 0x1ffff) == 0x208b)
 132         {
 133           #include "insns/lhseg_v.h"
 134           break;
 135         }
 136         if((insn.bits & 0x1ffff) == 0x108b)
 137         {
 138           #include "insns/lhst_v.h"
 139           break;
 140         }
 141         if((insn.bits & 0x3fffff) == 0x1008b)
 142         {
 143           #include "insns/mov_sv.h"
 144           break;
 145         }
 146         if((insn.bits & 0x3fffff) == 0x1808b)
 147         {
 148           #include "insns/fmov_sv.h"
 149           break;
 150         }
 151         if((insn.bits & 0x3fffff) == 0x8b)
 152         {
 153           #include "insns/lh_v.h"
 154           break;
 155         }
 156         if((insn.bits & 0x3fffff) == 0x88b)
 157         {
 158           #include "insns/sh_v.h"
 159           break;
 160         }
 161         if((insn.bits & 0x1ffff) == 0x288b)
 162         {
 163           #include "insns/shseg_v.h"
 164           break;
 165         }
 166         if((insn.bits & 0x1ffff) == 0x188b)
 167         {
 168           #include "insns/shst_v.h"
 169           break;
 170         }
 171         throw trap_illegal_instruction;
 172       }
 173       case 0x2:
 174       {
 175         if((insn.bits & 0x3fffff) == 0x10b)
 176         {
 177           #include "insns/lw_v.h"
 178           break;
 179         }
 180         if((insn.bits & 0x1ffff) == 0x1810b)
 181         {
 182           #include "insns/fmov_su.h"
 183           break;
 184         }
 185         if((insn.bits & 0x1ffff) == 0x290b)
 186         {
 187           #include "insns/swseg_v.h"
 188           break;
 189         }
 190         if((insn.bits & 0x1ffff) == 0x1010b)
 191         {
 192           #include "insns/mov_su.h"
 193           break;
 194         }
 195         if((insn.bits & 0x1ffff) == 0x1d0b)
 196         {
 197           #include "insns/fswst_v.h"
 198           break;
 199         }
 200         if((insn.bits & 0x1ffff) == 0x190b)
 201         {
 202           #include "insns/swst_v.h"
 203           break;
 204         }
 205         if((insn.bits & 0x3fffff) == 0xd0b)
 206         {
 207           #include "insns/fsw_v.h"
 208           break;
 209         }
 210         if((insn.bits & 0x1ffff) == 0x250b)
 211         {
 212           #include "insns/flwseg_v.h"
 213           break;
 214         }
 215         if((insn.bits & 0x3fffff) == 0x50b)
 216         {
 217           #include "insns/flw_v.h"
 218           break;
 219         }
 220         if((insn.bits & 0x3fffff) == 0x90b)
 221         {
 222           #include "insns/sw_v.h"
 223           break;
 224         }
 225         if((insn.bits & 0x1ffff) == 0x150b)
 226         {
 227           #include "insns/flwst_v.h"
 228           break;
 229         }
 230         if((insn.bits & 0x1ffff) == 0x210b)
 231         {
 232           #include "insns/lwseg_v.h"
 233           break;
 234         }
 235         if((insn.bits & 0x1ffff) == 0x2d0b)
 236         {
 237           #include "insns/fswseg_v.h"
 238           break;
 239         }
 240         if((insn.bits & 0x1ffff) == 0x110b)
 241         {
 242           #include "insns/lwst_v.h"
 243           break;
 244         }
 245         throw trap_illegal_instruction;
 246       }
 247       case 0x3:
 248       {
 249         if((insn.bits & 0x1ffff) == 0x218b)
 250         {
 251           #include "insns/ldseg_v.h"
 252           break;
 253         }
 254         if((insn.bits & 0x3fffff) == 0x58b)
 255         {
 256           #include "insns/fld_v.h"
 257           break;
 258         }
 259         if((insn.bits & 0x3fffff) == 0x18b)
 260         {
 261           #include "insns/ld_v.h"
 262           break;
 263         }
 264         if((insn.bits & 0x3fffff) == 0xd8b)
 265         {
 266           #include "insns/fsd_v.h"
 267           break;
 268         }
 269         if((insn.bits & 0x1ffff) == 0x2d8b)
 270         {
 271           #include "insns/fsdseg_v.h"
 272           break;
 273         }
 274         if((insn.bits & 0x1ffff) == 0x1d8b)
 275         {
 276           #include "insns/fsdst_v.h"
 277           break;
 278         }
 279         if((insn.bits & 0x1ffff) == 0x118b)
 280         {
 281           #include "insns/ldst_v.h"
 282           break;
 283         }
 284         if((insn.bits & 0x1ffff) == 0x258b)
 285         {
 286           #include "insns/fldseg_v.h"
 287           break;
 288         }
 289         if((insn.bits & 0x1ffff) == 0x1018b)
 290         {
 291           #include "insns/mov_us.h"
 292           break;
 293         }
 294         if((insn.bits & 0x1ffff) == 0x158b)
 295         {
 296           #include "insns/fldst_v.h"
 297           break;
 298         }
 299         if((insn.bits & 0x1ffff) == 0x298b)
 300         {
 301           #include "insns/sdseg_v.h"
 302           break;
 303         }
 304         if((insn.bits & 0x1ffff) == 0x1818b)
 305         {
 306           #include "insns/fmov_us.h"
 307           break;
 308         }
 309         if((insn.bits & 0x3fffff) == 0x98b)
 310         {
 311           #include "insns/sd_v.h"
 312           break;
 313         }
 314         if((insn.bits & 0x1ffff) == 0x198b)
 315         {
 316           #include "insns/sdst_v.h"
 317           break;
 318         }
 319         throw trap_illegal_instruction;
 320       }
 321       case 0x4:
 322       {
 323         if((insn.bits & 0x3fffff) == 0x20b)
 324         {
 325           #include "insns/lbu_v.h"
 326           break;
 327         }
 328         if((insn.bits & 0x1ffff) == 0x220b)
 329         {
 330           #include "insns/lbuseg_v.h"
 331           break;
 332         }
 333         if((insn.bits & 0x1ffff) == 0x120b)
 334         {
 335           #include "insns/lbust_v.h"
 336           break;
 337         }
 338         throw trap_illegal_instruction;
 339       }
 340       case 0x5:
 341       {
 342         if((insn.bits & 0x1ffff) == 0x128b)
 343         {
 344           #include "insns/lhust_v.h"
 345           break;
 346         }
 347         if((insn.bits & 0x3fffff) == 0x28b)
 348         {
 349           #include "insns/lhu_v.h"
 350           break;
 351         }
 352         if((insn.bits & 0x1ffff) == 0x228b)
 353         {
 354           #include "insns/lhuseg_v.h"
 355           break;
 356         }
 357         throw trap_illegal_instruction;
 358       }
 359       case 0x6:
 360       {
 361         if((insn.bits & 0x1ffff) == 0x230b)
 362         {
 363           #include "insns/lwuseg_v.h"
 364           break;
 365         }
 366         if((insn.bits & 0x3fffff) == 0x30b)
 367         {
 368           #include "insns/lwu_v.h"
 369           break;
 370         }
 371         if((insn.bits & 0x1ffff) == 0x130b)
 372         {
 373           #include "insns/lwust_v.h"
 374           break;
 375         }
 376         throw trap_illegal_instruction;
 377       }
 378       default:
 379       {
 380         throw trap_illegal_instruction;
 381       }
 382     }
 383     break;
 384   }
 385   case 0xf:
 386   {
 387     switch((insn.bits >> 0x7) & 0x7)
 388     {
 389       case 0x0:
 390       {
 391         if((insn.bits & 0xfff) == 0x80f)
 392         {
 393           #include "insns/sbsegst_v.h"
 394           break;
 395         }
 396         if((insn.bits & 0xfff) == 0xf)
 397         {
 398           #include "insns/lbsegst_v.h"
 399           break;
 400         }
 401         throw trap_illegal_instruction;
 402       }
 403       case 0x1:
 404       {
 405         if((insn.bits & 0xfff) == 0x88f)
 406         {
 407           #include "insns/shsegst_v.h"
 408           break;
 409         }
 410         if((insn.bits & 0xfff) == 0x8f)
 411         {
 412           #include "insns/lhsegst_v.h"
 413           break;
 414         }
 415         throw trap_illegal_instruction;
 416       }
 417       case 0x2:
 418       {
 419         if((insn.bits & 0xfff) == 0xd0f)
 420         {
 421           #include "insns/fswsegst_v.h"
 422           break;
 423         }
 424         if((insn.bits & 0xfff) == 0x50f)
 425         {
 426           #include "insns/flwsegst_v.h"
 427           break;
 428         }
 429         if((insn.bits & 0xfff) == 0x10f)
 430         {
 431           #include "insns/lwsegst_v.h"
 432           break;
 433         }
 434         if((insn.bits & 0xfff) == 0x90f)
 435         {
 436           #include "insns/swsegst_v.h"
 437           break;
 438         }
 439         throw trap_illegal_instruction;
 440       }
 441       case 0x3:
 442       {
 443         if((insn.bits & 0xfff) == 0x18f)
 444         {
 445           #include "insns/ldsegst_v.h"
 446           break;
 447         }
 448         if((insn.bits & 0xfff) == 0x98f)
 449         {
 450           #include "insns/sdsegst_v.h"
 451           break;
 452         }
 453         if((insn.bits & 0xfff) == 0x58f)
 454         {
 455           #include "insns/fldsegst_v.h"
 456           break;
 457         }
 458         if((insn.bits & 0xfff) == 0xd8f)
 459         {
 460           #include "insns/fsdsegst_v.h"
 461           break;
 462         }
 463         throw trap_illegal_instruction;
 464       }
 465       case 0x4:
 466       {
 467         if((insn.bits & 0xfff) == 0x20f)
 468         {
 469           #include "insns/lbusegst_v.h"
 470           break;
 471         }
 472         throw trap_illegal_instruction;
 473       }
 474       case 0x5:
 475       {
 476         if((insn.bits & 0xfff) == 0x28f)
 477         {
 478           #include "insns/lhusegst_v.h"
 479           break;
 480         }
 481         throw trap_illegal_instruction;
 482       }
 483       case 0x6:
 484       {
 485         if((insn.bits & 0xfff) == 0x30f)
 486         {
 487           #include "insns/lwusegst_v.h"
 488           break;
 489         }
 490         throw trap_illegal_instruction;
 491       }
 492       default:
 493       {
 494         throw trap_illegal_instruction;
 495       }
 496     }
 497     break;
 498   }
 499   case 0x13:
 500   {
 501     switch((insn.bits >> 0x7) & 0x7)
 502     {
 503       case 0x0:
 504       {
 505         #include "insns/addi.h"
 506         break;
 507       }
 508       case 0x1:
 509       {
 510         if((insn.bits & 0x3f03ff) == 0x93)
 511         {
 512           #include "insns/slli.h"
 513           break;
 514         }
 515         throw trap_illegal_instruction;
 516       }
 517       case 0x2:
 518       {
 519         #include "insns/slti.h"
 520         break;
 521       }
 522       case 0x3:
 523       {
 524         #include "insns/sltiu.h"
 525         break;
 526       }
 527       case 0x4:
 528       {
 529         #include "insns/xori.h"
 530         break;
 531       }
 532       case 0x5:
 533       {
 534         if((insn.bits & 0x3f03ff) == 0x293)
 535         {
 536           #include "insns/srli.h"
 537           break;
 538         }
 539         if((insn.bits & 0x3f03ff) == 0x10293)
 540         {
 541           #include "insns/srai.h"
 542           break;
 543         }
 544         throw trap_illegal_instruction;
 545       }
 546       case 0x6:
 547       {
 548         #include "insns/ori.h"
 549         break;
 550       }
 551       case 0x7:
 552       {
 553         #include "insns/andi.h"
 554         break;
 555       }
 556       default:
 557       {
 558         throw trap_illegal_instruction;
 559       }
 560     }
 561     break;
 562   }
 563   case 0x1b:
 564   {
 565     switch((insn.bits >> 0x7) & 0x7)
 566     {
 567       case 0x0:
 568       {
 569         #include "insns/addiw.h"
 570         break;
 571       }
 572       case 0x1:
 573       {
 574         if((insn.bits & 0x3f83ff) == 0x9b)
 575         {
 576           #include "insns/slliw.h"
 577           break;
 578         }
 579         throw trap_illegal_instruction;
 580       }
 581       case 0x5:
 582       {
 583         if((insn.bits & 0x3f83ff) == 0x29b)
 584         {
 585           #include "insns/srliw.h"
 586           break;
 587         }
 588         if((insn.bits & 0x3f83ff) == 0x1029b)
 589         {
 590           #include "insns/sraiw.h"
 591           break;
 592         }
 593         throw trap_illegal_instruction;
 594       }
 595       default:
 596       {
 597         throw trap_illegal_instruction;
 598       }
 599     }
 600     break;
 601   }
 602   case 0x20:
 603   {
 604     #include "insns/c_addi.h"
 605     break;
 606   }
 607   case 0x21:
 608   {
 609     #include "insns/c_li.h"
 610     break;
 611   }
 612   case 0x23:
 613   {
 614     switch((insn.bits >> 0x7) & 0x7)
 615     {
 616       case 0x0:
 617       {
 618         #include "insns/sb.h"
 619         break;
 620       }
 621       case 0x1:
 622       {
 623         #include "insns/sh.h"
 624         break;
 625       }
 626       case 0x2:
 627       {
 628         #include "insns/sw.h"
 629         break;
 630       }
 631       case 0x3:
 632       {
 633         #include "insns/sd.h"
 634         break;
 635       }
 636       default:
 637       {
 638         throw trap_illegal_instruction;
 639       }
 640     }
 641     break;
 642   }
 643   case 0x27:
 644   {
 645     switch((insn.bits >> 0x7) & 0x7)
 646     {
 647       case 0x2:
 648       {
 649         #include "insns/fsw.h"
 650         break;
 651       }
 652       case 0x3:
 653       {
 654         #include "insns/fsd.h"
 655         break;
 656       }
 657       default:
 658       {
 659         throw trap_illegal_instruction;
 660       }
 661     }
 662     break;
 663   }
 664   case 0x2b:
 665   {
 666     switch((insn.bits >> 0x7) & 0x7)
 667     {
 668       case 0x2:
 669       {
 670         if((insn.bits & 0x1ffff) == 0x192b)
 671         {
 672           #include "insns/amominu_w.h"
 673           break;
 674         }
 675         if((insn.bits & 0x1ffff) == 0x92b)
 676         {
 677           #include "insns/amoand_w.h"
 678           break;
 679         }
 680         if((insn.bits & 0x1ffff) == 0x1d2b)
 681         {
 682           #include "insns/amomaxu_w.h"
 683           break;
 684         }
 685         if((insn.bits & 0x1ffff) == 0x152b)
 686         {
 687           #include "insns/amomax_w.h"
 688           break;
 689         }
 690         if((insn.bits & 0x1ffff) == 0x12b)
 691         {
 692           #include "insns/amoadd_w.h"
 693           break;
 694         }
 695         if((insn.bits & 0x1ffff) == 0xd2b)
 696         {
 697           #include "insns/amoor_w.h"
 698           break;
 699         }
 700         if((insn.bits & 0x1ffff) == 0x112b)
 701         {
 702           #include "insns/amomin_w.h"
 703           break;
 704         }
 705         if((insn.bits & 0x1ffff) == 0x52b)
 706         {
 707           #include "insns/amoswap_w.h"
 708           break;
 709         }
 710         throw trap_illegal_instruction;
 711       }
 712       case 0x3:
 713       {
 714         if((insn.bits & 0x1ffff) == 0x19ab)
 715         {
 716           #include "insns/amominu_d.h"
 717           break;
 718         }
 719         if((insn.bits & 0x1ffff) == 0x9ab)
 720         {
 721           #include "insns/amoand_d.h"
 722           break;
 723         }
 724         if((insn.bits & 0x1ffff) == 0x1dab)
 725         {
 726           #include "insns/amomaxu_d.h"
 727           break;
 728         }
 729         if((insn.bits & 0x1ffff) == 0x1ab)
 730         {
 731           #include "insns/amoadd_d.h"
 732           break;
 733         }
 734         if((insn.bits & 0x1ffff) == 0x15ab)
 735         {
 736           #include "insns/amomax_d.h"
 737           break;
 738         }
 739         if((insn.bits & 0x1ffff) == 0xdab)
 740         {
 741           #include "insns/amoor_d.h"
 742           break;
 743         }
 744         if((insn.bits & 0x1ffff) == 0x5ab)
 745         {
 746           #include "insns/amoswap_d.h"
 747           break;
 748         }
 749         if((insn.bits & 0x1ffff) == 0x11ab)
 750         {
 751           #include "insns/amomin_d.h"
 752           break;
 753         }
 754         throw trap_illegal_instruction;
 755       }
 756       default:
 757       {
 758         throw trap_illegal_instruction;
 759       }
 760     }
 761     break;
 762   }
 763   case 0x2f:
 764   {
 765     switch((insn.bits >> 0x7) & 0x7)
 766     {
 767       case 0x1:
 768       {
 769         #include "insns/fence_i.h"
 770         break;
 771       }
 772       case 0x2:
 773       {
 774         #include "insns/fence.h"
 775         break;
 776       }
 777       case 0x4:
 778       {
 779         #include "insns/fence_l_v.h"
 780         break;
 781       }
 782       case 0x5:
 783       {
 784         #include "insns/fence_g_v.h"
 785         break;
 786       }
 787       case 0x6:
 788       {
 789         #include "insns/fence_l_cv.h"
 790         break;
 791       }
 792       case 0x7:
 793       {
 794         #include "insns/fence_g_cv.h"
 795         break;
 796       }
 797       default:
 798       {
 799         throw trap_illegal_instruction;
 800       }
 801     }
 802     break;
 803   }
 804   case 0x33:
 805   {
 806     switch((insn.bits >> 0x7) & 0x7)
 807     {
 808       case 0x0:
 809       {
 810         if((insn.bits & 0x1ffff) == 0x33)
 811         {
 812           #include "insns/add.h"
 813           break;
 814         }
 815         if((insn.bits & 0x1ffff) == 0x433)
 816         {
 817           #include "insns/mul.h"
 818           break;
 819         }
 820         if((insn.bits & 0x1ffff) == 0x10033)
 821         {
 822           #include "insns/sub.h"
 823           break;
 824         }
 825         throw trap_illegal_instruction;
 826       }
 827       case 0x1:
 828       {
 829         if((insn.bits & 0x1ffff) == 0xb3)
 830         {
 831           #include "insns/sll.h"
 832           break;
 833         }
 834         if((insn.bits & 0x1ffff) == 0x4b3)
 835         {
 836           #include "insns/mulh.h"
 837           break;
 838         }
 839         throw trap_illegal_instruction;
 840       }
 841       case 0x2:
 842       {
 843         if((insn.bits & 0x1ffff) == 0x533)
 844         {
 845           #include "insns/mulhsu.h"
 846           break;
 847         }
 848         if((insn.bits & 0x1ffff) == 0x133)
 849         {
 850           #include "insns/slt.h"
 851           break;
 852         }
 853         throw trap_illegal_instruction;
 854       }
 855       case 0x3:
 856       {
 857         if((insn.bits & 0x1ffff) == 0x1b3)
 858         {
 859           #include "insns/sltu.h"
 860           break;
 861         }
 862         if((insn.bits & 0x1ffff) == 0x5b3)
 863         {
 864           #include "insns/mulhu.h"
 865           break;
 866         }
 867         throw trap_illegal_instruction;
 868       }
 869       case 0x4:
 870       {
 871         if((insn.bits & 0x1ffff) == 0x633)
 872         {
 873           #include "insns/div.h"
 874           break;
 875         }
 876         if((insn.bits & 0x1ffff) == 0x233)
 877         {
 878           #include "insns/xor.h"
 879           break;
 880         }
 881         throw trap_illegal_instruction;
 882       }
 883       case 0x5:
 884       {
 885         if((insn.bits & 0x1ffff) == 0x102b3)
 886         {
 887           #include "insns/sra.h"
 888           break;
 889         }
 890         if((insn.bits & 0x1ffff) == 0x2b3)
 891         {
 892           #include "insns/srl.h"
 893           break;
 894         }
 895         if((insn.bits & 0x1ffff) == 0x6b3)
 896         {
 897           #include "insns/divu.h"
 898           break;
 899         }
 900         throw trap_illegal_instruction;
 901       }
 902       case 0x6:
 903       {
 904         if((insn.bits & 0x1ffff) == 0x733)
 905         {
 906           #include "insns/rem.h"
 907           break;
 908         }
 909         if((insn.bits & 0x1ffff) == 0x333)
 910         {
 911           #include "insns/or.h"
 912           break;
 913         }
 914         throw trap_illegal_instruction;
 915       }
 916       case 0x7:
 917       {
 918         if((insn.bits & 0x1ffff) == 0x7b3)
 919         {
 920           #include "insns/remu.h"
 921           break;
 922         }
 923         if((insn.bits & 0x1ffff) == 0x3b3)
 924         {
 925           #include "insns/and.h"
 926           break;
 927         }
 928         throw trap_illegal_instruction;
 929       }
 930       default:
 931       {
 932         throw trap_illegal_instruction;
 933       }
 934     }
 935     break;
 936   }
 937   case 0x37:
 938   {
 939     #include "insns/lui.h"
 940     break;
 941   }
 942   case 0x3b:
 943   {
 944     switch((insn.bits >> 0x7) & 0x7)
 945     {
 946       case 0x0:
 947       {
 948         if((insn.bits & 0x1ffff) == 0x43b)
 949         {
 950           #include "insns/mulw.h"
 951           break;
 952         }
 953         if((insn.bits & 0x1ffff) == 0x3b)
 954         {
 955           #include "insns/addw.h"
 956           break;
 957         }
 958         if((insn.bits & 0x1ffff) == 0x1003b)
 959         {
 960           #include "insns/subw.h"
 961           break;
 962         }
 963         throw trap_illegal_instruction;
 964       }
 965       case 0x1:
 966       {
 967         if((insn.bits & 0x1ffff) == 0xbb)
 968         {
 969           #include "insns/sllw.h"
 970           break;
 971         }
 972         throw trap_illegal_instruction;
 973       }
 974       case 0x4:
 975       {
 976         if((insn.bits & 0x1ffff) == 0x63b)
 977         {
 978           #include "insns/divw.h"
 979           break;
 980         }
 981         throw trap_illegal_instruction;
 982       }
 983       case 0x5:
 984       {
 985         if((insn.bits & 0x1ffff) == 0x6bb)
 986         {
 987           #include "insns/divuw.h"
 988           break;
 989         }
 990         if((insn.bits & 0x1ffff) == 0x2bb)
 991         {
 992           #include "insns/srlw.h"
 993           break;
 994         }
 995         if((insn.bits & 0x1ffff) == 0x102bb)
 996         {
 997           #include "insns/sraw.h"
 998           break;
 999         }
1000         throw trap_illegal_instruction;
1001       }
1002       case 0x6:
1003       {
1004         if((insn.bits & 0x1ffff) == 0x73b)
1005         {
1006           #include "insns/remw.h"
1007           break;
1008         }
1009         throw trap_illegal_instruction;
1010       }
1011       case 0x7:
1012       {
1013         if((insn.bits & 0x1ffff) == 0x7bb)
1014         {
1015           #include "insns/remuw.h"
1016           break;
1017         }
1018         throw trap_illegal_instruction;
1019       }
1020       default:
1021       {
1022         throw trap_illegal_instruction;
1023       }
1024     }
1025     break;
1026   }
1027   case 0x40:
1028   {
1029     #include "insns/c_addi.h"
1030     break;
1031   }
1032   case 0x41:
1033   {
1034     #include "insns/c_li.h"
1035     break;
1036   }
1037   case 0x43:
1038   {
1039     switch((insn.bits >> 0x7) & 0x7)
1040     {
1041       case 0x0:
1042       {
1043         #include "insns/fmadd_s.h"
1044         break;
1045       }
1046       case 0x1:
1047       {
1048         #include "insns/fmadd_d.h"
1049         break;
1050       }
1051       case 0x4:
1052       {
1053         #include "insns/fmadd_s.h"
1054         break;
1055       }
1056       case 0x5:
1057       {
1058         #include "insns/fmadd_d.h"
1059         break;
1060       }
1061       default:
1062       {
1063         throw trap_illegal_instruction;
1064       }
1065     }
1066     break;
1067   }
1068   case 0x47:
1069   {
1070     switch((insn.bits >> 0x7) & 0x7)
1071     {
1072       case 0x0:
1073       {
1074         #include "insns/fmsub_s.h"
1075         break;
1076       }
1077       case 0x1:
1078       {
1079         #include "insns/fmsub_d.h"
1080         break;
1081       }
1082       case 0x4:
1083       {
1084         #include "insns/fmsub_s.h"
1085         break;
1086       }
1087       case 0x5:
1088       {
1089         #include "insns/fmsub_d.h"
1090         break;
1091       }
1092       default:
1093       {
1094         throw trap_illegal_instruction;
1095       }
1096     }
1097     break;
1098   }
1099   case 0x4b:
1100   {
1101     switch((insn.bits >> 0x7) & 0x7)
1102     {
1103       case 0x0:
1104       {
1105         #include "insns/fnmsub_s.h"
1106         break;
1107       }
1108       case 0x1:
1109       {
1110         #include "insns/fnmsub_d.h"
1111         break;
1112       }
1113       case 0x4:
1114       {
1115         #include "insns/fnmsub_s.h"
1116         break;
1117       }
1118       case 0x5:
1119       {
1120         #include "insns/fnmsub_d.h"
1121         break;
1122       }
1123       default:
1124       {
1125         throw trap_illegal_instruction;
1126       }
1127     }
1128     break;
1129   }
1130   case 0x4f:
1131   {
1132     switch((insn.bits >> 0x7) & 0x7)
1133     {
1134       case 0x0:
1135       {
1136         #include "insns/fnmadd_s.h"
1137         break;
1138       }
1139       case 0x1:
1140       {
1141         #include "insns/fnmadd_d.h"
1142         break;
1143       }
1144       case 0x4:
1145       {
1146         #include "insns/fnmadd_s.h"
1147         break;
1148       }
1149       case 0x5:
1150       {
1151         #include "insns/fnmadd_d.h"
1152         break;
1153       }
1154       default:
1155       {
1156         throw trap_illegal_instruction;
1157       }
1158     }
1159     break;
1160   }
1161   case 0x53:
1162   {
1163     switch((insn.bits >> 0x7) & 0x7)
1164     {
1165       case 0x0:
1166       {
1167         if((insn.bits & 0x3ff1ff) == 0x9053)
1168         {
1169           #include "insns/fcvt_lu_s.h"
1170           break;
1171         }
1172         if((insn.bits & 0x1ffff) == 0x18053)
1173         {
1174           #include "insns/fmin_s.h"
1175           break;
1176         }
1177         if((insn.bits & 0x3ff1ff) == 0x11053)
1178         {
1179           #include "insns/fcvt_s_d.h"
1180           break;
1181         }
1182         if((insn.bits & 0x3ff1ff) == 0xe053)
1183         {
1184           #include "insns/fcvt_s_w.h"
1185           break;
1186         }
1187         if((insn.bits & 0x7c1ffff) == 0x1c053)
1188         {
1189           #include "insns/mftx_s.h"
1190           break;
1191         }
1192         if((insn.bits & 0x3ff1ff) == 0x8053)
1193         {
1194           #include "insns/fcvt_l_s.h"
1195           break;
1196         }
1197         if((insn.bits & 0x1ffff) == 0x17053)
1198         {
1199           #include "insns/fle_s.h"
1200           break;
1201         }
1202         if((insn.bits & 0x7ffffff) == 0x1d053)
1203         {
1204           #include "insns/mffsr.h"
1205           break;
1206         }
1207         if((insn.bits & 0x1f1ff) == 0x3053)
1208         {
1209           #include "insns/fdiv_s.h"
1210           break;
1211         }
1212         if((insn.bits & 0x3fffff) == 0x1f053)
1213         {
1214           #include "insns/mtfsr.h"
1215           break;
1216         }
1217         if((insn.bits & 0x3ff1ff) == 0xd053)
1218         {
1219           #include "insns/fcvt_s_lu.h"
1220           break;
1221         }
1222         if((insn.bits & 0x1f1ff) == 0x2053)
1223         {
1224           #include "insns/fmul_s.h"
1225           break;
1226         }
1227         if((insn.bits & 0x1ffff) == 0x16053)
1228         {
1229           #include "insns/flt_s.h"
1230           break;
1231         }
1232         if((insn.bits & 0x1ffff) == 0x15053)
1233         {
1234           #include "insns/feq_s.h"
1235           break;
1236         }
1237         if((insn.bits & 0x1ffff) == 0x7053)
1238         {
1239           #include "insns/fsgnjx_s.h"
1240           break;
1241         }
1242         if((insn.bits & 0x1ffff) == 0x19053)
1243         {
1244           #include "insns/fmax_s.h"
1245           break;
1246         }
1247         if((insn.bits & 0x3ff1ff) == 0xb053)
1248         {
1249           #include "insns/fcvt_wu_s.h"
1250           break;
1251         }
1252         if((insn.bits & 0x3ff1ff) == 0xa053)
1253         {
1254           #include "insns/fcvt_w_s.h"
1255           break;
1256         }
1257         if((insn.bits & 0x3fffff) == 0x1e053)
1258         {
1259           #include "insns/mxtf_s.h"
1260           break;
1261         }
1262         if((insn.bits & 0x1f1ff) == 0x1053)
1263         {
1264           #include "insns/fsub_s.h"
1265           break;
1266         }
1267         if((insn.bits & 0x1ffff) == 0x5053)
1268         {
1269           #include "insns/fsgnj_s.h"
1270           break;
1271         }
1272         if((insn.bits & 0x3ff1ff) == 0xf053)
1273         {
1274           #include "insns/fcvt_s_wu.h"
1275           break;
1276         }
1277         if((insn.bits & 0x3ff1ff) == 0xc053)
1278         {
1279           #include "insns/fcvt_s_l.h"
1280           break;
1281         }
1282         if((insn.bits & 0x3ff1ff) == 0x4053)
1283         {
1284           #include "insns/fsqrt_s.h"
1285           break;
1286         }
1287         if((insn.bits & 0x1ffff) == 0x6053)
1288         {
1289           #include "insns/fsgnjn_s.h"
1290           break;
1291         }
1292         if((insn.bits & 0x1f1ff) == 0x53)
1293         {
1294           #include "insns/fadd_s.h"
1295           break;
1296         }
1297         throw trap_illegal_instruction;
1298       }
1299       case 0x1:
1300       {
1301         if((insn.bits & 0x1ffff) == 0x180d3)
1302         {
1303           #include "insns/fmin_d.h"
1304           break;
1305         }
1306         if((insn.bits & 0x3ff1ff) == 0xc0d3)
1307         {
1308           #include "insns/fcvt_d_l.h"
1309           break;
1310         }
1311         if((insn.bits & 0x3fffff) == 0xe0d3)
1312         {
1313           #include "insns/fcvt_d_w.h"
1314           break;
1315         }
1316         if((insn.bits & 0x3fffff) == 0x100d3)
1317         {
1318           #include "insns/fcvt_d_s.h"
1319           break;
1320         }
1321         if((insn.bits & 0x1ffff) == 0x190d3)
1322         {
1323           #include "insns/fmax_d.h"
1324           break;
1325         }
1326         if((insn.bits & 0x7c1ffff) == 0x1c0d3)
1327         {
1328           #include "insns/mftx_d.h"
1329           break;
1330         }
1331         if((insn.bits & 0x1ffff) == 0x170d3)
1332         {
1333           #include "insns/fle_d.h"
1334           break;
1335         }
1336         if((insn.bits & 0x1ffff) == 0x160d3)
1337         {
1338           #include "insns/flt_d.h"
1339           break;
1340         }
1341         if((insn.bits & 0x1f1ff) == 0x20d3)
1342         {
1343           #include "insns/fmul_d.h"
1344           break;
1345         }
1346         if((insn.bits & 0x1ffff) == 0x70d3)
1347         {
1348           #include "insns/fsgnjx_d.h"
1349           break;
1350         }
1351         if((insn.bits & 0x1ffff) == 0x150d3)
1352         {
1353           #include "insns/feq_d.h"
1354           break;
1355         }
1356         if((insn.bits & 0x3fffff) == 0xf0d3)
1357         {
1358           #include "insns/fcvt_d_wu.h"
1359           break;
1360         }
1361         if((insn.bits & 0x3ff1ff) == 0xb0d3)
1362         {
1363           #include "insns/fcvt_wu_d.h"
1364           break;
1365         }
1366         if((insn.bits & 0x1ffff) == 0x60d3)
1367         {
1368           #include "insns/fsgnjn_d.h"
1369           break;
1370         }
1371         if((insn.bits & 0x3ff1ff) == 0xd0d3)
1372         {
1373           #include "insns/fcvt_d_lu.h"
1374           break;
1375         }
1376         if((insn.bits & 0x3ff1ff) == 0xa0d3)
1377         {
1378           #include "insns/fcvt_w_d.h"
1379           break;
1380         }
1381         if((insn.bits & 0x3fffff) == 0x1e0d3)
1382         {
1383           #include "insns/mxtf_d.h"
1384           break;
1385         }
1386         if((insn.bits & 0x1ffff) == 0x50d3)
1387         {
1388           #include "insns/fsgnj_d.h"
1389           break;
1390         }
1391         if((insn.bits & 0x3ff1ff) == 0x80d3)
1392         {
1393           #include "insns/fcvt_l_d.h"
1394           break;
1395         }
1396         if((insn.bits & 0x1f1ff) == 0xd3)
1397         {
1398           #include "insns/fadd_d.h"
1399           break;
1400         }
1401         if((insn.bits & 0x3ff1ff) == 0x90d3)
1402         {
1403           #include "insns/fcvt_lu_d.h"
1404           break;
1405         }
1406         if((insn.bits & 0x1f1ff) == 0x10d3)
1407         {
1408           #include "insns/fsub_d.h"
1409           break;
1410         }
1411         if((insn.bits & 0x3ff1ff) == 0x40d3)
1412         {
1413           #include "insns/fsqrt_d.h"
1414           break;
1415         }
1416         if((insn.bits & 0x1f1ff) == 0x30d3)
1417         {
1418           #include "insns/fdiv_d.h"
1419           break;
1420         }
1421         throw trap_illegal_instruction;
1422       }
1423       case 0x4:
1424       {
1425         if((insn.bits & 0x3ff1ff) == 0x9053)
1426         {
1427           #include "insns/fcvt_lu_s.h"
1428           break;
1429         }
1430         if((insn.bits & 0x3ff1ff) == 0x11053)
1431         {
1432           #include "insns/fcvt_s_d.h"
1433           break;
1434         }
1435         if((insn.bits & 0x3ff1ff) == 0xe053)
1436         {
1437           #include "insns/fcvt_s_w.h"
1438           break;
1439         }
1440         if((insn.bits & 0x3ff1ff) == 0x8053)
1441         {
1442           #include "insns/fcvt_l_s.h"
1443           break;
1444         }
1445         if((insn.bits & 0x1f1ff) == 0x3053)
1446         {
1447           #include "insns/fdiv_s.h"
1448           break;
1449         }
1450         if((insn.bits & 0x3ff1ff) == 0xd053)
1451         {
1452           #include "insns/fcvt_s_lu.h"
1453           break;
1454         }
1455         if((insn.bits & 0x1f1ff) == 0x2053)
1456         {
1457           #include "insns/fmul_s.h"
1458           break;
1459         }
1460         if((insn.bits & 0x3ff1ff) == 0xb053)
1461         {
1462           #include "insns/fcvt_wu_s.h"
1463           break;
1464         }
1465         if((insn.bits & 0x3ff1ff) == 0xa053)
1466         {
1467           #include "insns/fcvt_w_s.h"
1468           break;
1469         }
1470         if((insn.bits & 0x1f1ff) == 0x1053)
1471         {
1472           #include "insns/fsub_s.h"
1473           break;
1474         }
1475         if((insn.bits & 0x3ff1ff) == 0xf053)
1476         {
1477           #include "insns/fcvt_s_wu.h"
1478           break;
1479         }
1480         if((insn.bits & 0x3ff1ff) == 0xc053)
1481         {
1482           #include "insns/fcvt_s_l.h"
1483           break;
1484         }
1485         if((insn.bits & 0x3ff1ff) == 0x4053)
1486         {
1487           #include "insns/fsqrt_s.h"
1488           break;
1489         }
1490         if((insn.bits & 0x1f1ff) == 0x53)
1491         {
1492           #include "insns/fadd_s.h"
1493           break;
1494         }
1495         throw trap_illegal_instruction;
1496       }
1497       case 0x5:
1498       {
1499         if((insn.bits & 0x3ff1ff) == 0xc0d3)
1500         {
1501           #include "insns/fcvt_d_l.h"
1502           break;
1503         }
1504         if((insn.bits & 0x1f1ff) == 0x20d3)
1505         {
1506           #include "insns/fmul_d.h"
1507           break;
1508         }
1509         if((insn.bits & 0x3ff1ff) == 0xb0d3)
1510         {
1511           #include "insns/fcvt_wu_d.h"
1512           break;
1513         }
1514         if((insn.bits & 0x3ff1ff) == 0xd0d3)
1515         {
1516           #include "insns/fcvt_d_lu.h"
1517           break;
1518         }
1519         if((insn.bits & 0x3ff1ff) == 0xa0d3)
1520         {
1521           #include "insns/fcvt_w_d.h"
1522           break;
1523         }
1524         if((insn.bits & 0x3ff1ff) == 0x80d3)
1525         {
1526           #include "insns/fcvt_l_d.h"
1527           break;
1528         }
1529         if((insn.bits & 0x1f1ff) == 0xd3)
1530         {
1531           #include "insns/fadd_d.h"
1532           break;
1533         }
1534         if((insn.bits & 0x3ff1ff) == 0x90d3)
1535         {
1536           #include "insns/fcvt_lu_d.h"
1537           break;
1538         }
1539         if((insn.bits & 0x1f1ff) == 0x10d3)
1540         {
1541           #include "insns/fsub_d.h"
1542           break;
1543         }
1544         if((insn.bits & 0x3ff1ff) == 0x40d3)
1545         {
1546           #include "insns/fsqrt_d.h"
1547           break;
1548         }
1549         if((insn.bits & 0x1f1ff) == 0x30d3)
1550         {
1551           #include "insns/fdiv_d.h"
1552           break;
1553         }
1554         throw trap_illegal_instruction;
1555       }
1556       default:
1557       {
1558         throw trap_illegal_instruction;
1559       }
1560     }
1561     break;
1562   }
1563   case 0x60:
1564   {
1565     #include "insns/c_addi.h"
1566     break;
1567   }
1568   case 0x61:
1569   {
1570     #include "insns/c_li.h"
1571     break;
1572   }
1573   case 0x63:
1574   {
1575     switch((insn.bits >> 0x7) & 0x7)
1576     {
1577       case 0x0:
1578       {
1579         #include "insns/beq.h"
1580         break;
1581       }
1582       case 0x1:
1583       {
1584         #include "insns/bne.h"
1585         break;
1586       }
1587       case 0x4:
1588       {
1589         #include "insns/blt.h"
1590         break;
1591       }
1592       case 0x5:
1593       {
1594         #include "insns/bge.h"
1595         break;
1596       }
1597       case 0x6:
1598       {
1599         #include "insns/bltu.h"
1600         break;
1601       }
1602       case 0x7:
1603       {
1604         #include "insns/bgeu.h"
1605         break;
1606       }
1607       default:
1608       {
1609         throw trap_illegal_instruction;
1610       }
1611     }
1612     break;
1613   }
1614   case 0x67:
1615   {
1616     #include "insns/j.h"
1617     break;
1618   }
1619   case 0x6b:
1620   {
1621     switch((insn.bits >> 0x7) & 0x7)
1622     {
1623       case 0x0:
1624       {
1625         #include "insns/jalr_c.h"
1626         break;
1627       }
1628       case 0x1:
1629       {
1630         #include "insns/jalr_r.h"
1631         break;
1632       }
1633       case 0x2:
1634       {
1635         #include "insns/jalr_j.h"
1636         break;
1637       }
1638       case 0x4:
1639       {
1640         if((insn.bits & 0x7ffffff) == 0x26b)
1641         {
1642           #include "insns/rdnpc.h"
1643           break;
1644         }
1645         throw trap_illegal_instruction;
1646       }
1647       default:
1648       {
1649         throw trap_illegal_instruction;
1650       }
1651     }
1652     break;
1653   }
1654   case 0x6f:
1655   {
1656     #include "insns/jal.h"
1657     break;
1658   }
1659   case 0x73:
1660   {
1661     switch((insn.bits >> 0x7) & 0x7)
1662     {
1663       case 0x0:
1664       {
1665         #include "insns/vcfgivl.h"
1666         break;
1667       }
1668       case 0x1:
1669       {
1670         if((insn.bits & 0x3fffff) == 0xf3)
1671         {
1672           #include "insns/setvl.h"
1673           break;
1674         }
1675         throw trap_illegal_instruction;
1676       }
1677       case 0x2:
1678       {
1679         if((insn.bits & 0xf80003ff) == 0x173)
1680         {
1681           #include "insns/vf.h"
1682           break;
1683         }
1684         throw trap_illegal_instruction;
1685       }
1686       default:
1687       {
1688         throw trap_illegal_instruction;
1689       }
1690     }
1691     break;
1692   }
1693   case 0x77:
1694   {
1695     switch((insn.bits >> 0x7) & 0x7)
1696     {
1697       case 0x0:
1698       {
1699         if((insn.bits & 0xffffffff) == 0x77)
1700         {
1701           #include "insns/syscall.h"
1702           break;
1703         }
1704         throw trap_illegal_instruction;
1705       }
1706       case 0x1:
1707       {
1708         if((insn.bits & 0xffffffff) == 0xf7)
1709         {
1710           #include "insns/break.h"
1711           break;
1712         }
1713         throw trap_illegal_instruction;
1714       }
1715       case 0x2:
1716       {
1717         if((insn.bits & 0xffffffff) == 0x177)
1718         {
1719           #include "insns/stop.h"
1720           break;
1721         }
1722         throw trap_illegal_instruction;
1723       }
1724       case 0x3:
1725       {
1726         if((insn.bits & 0x7ffffff) == 0x1f7)
1727         {
1728           #include "insns/utidx.h"
1729           break;
1730         }
1731         throw trap_illegal_instruction;
1732       }
1733       default:
1734       {
1735         throw trap_illegal_instruction;
1736       }
1737     }
1738     break;
1739   }
1740   case 0x7b:
1741   {
1742     switch((insn.bits >> 0x7) & 0x7)
1743     {
1744       case 0x0:
1745       {
1746         if((insn.bits & 0x7ffffff) == 0x7b)
1747         {
1748           #include "insns/ei.h"
1749           break;
1750         }
1751         throw trap_illegal_instruction;
1752       }
1753       case 0x1:
1754       {
1755         if((insn.bits & 0x7ffffff) == 0xfb)
1756         {
1757           #include "insns/di.h"
1758           break;
1759         }
1760         throw trap_illegal_instruction;
1761       }
1762       case 0x2:
1763       {
1764         if((insn.bits & 0x7c1ffff) == 0x17b)
1765         {
1766           #include "insns/mfpcr.h"
1767           break;
1768         }
1769         throw trap_illegal_instruction;
1770       }
1771       case 0x3:
1772       {
1773         if((insn.bits & 0xf801ffff) == 0x1fb)
1774         {
1775           #include "insns/mtpcr.h"
1776           break;
1777         }
1778         throw trap_illegal_instruction;
1779       }
1780       case 0x4:
1781       {
1782         if((insn.bits & 0xffffffff) == 0x27b)
1783         {
1784           #include "insns/eret.h"
1785           break;
1786         }
1787         throw trap_illegal_instruction;
1788       }
1789       default:
1790       {
1791         throw trap_illegal_instruction;
1792       }
1793     }
1794     break;
1795   }
1796   default:
1797   {
1798     throw trap_illegal_instruction;
1799   }
1800 }