cce8345121f61a9f2fe554d0f284b810977236f5
[riscv-isa-sim.git] / riscv / extension.h
1 #ifndef _RISCV_COPROCESSOR_H
2 #define _RISCV_COPROCESSOR_H
3
4 #include "processor.h"
5 #include "disasm.h"
6 #include <map>
7 #include <string>
8 #include <vector>
9 #include <functional>
10
11 class extension_t
12 {
13 public:
14 virtual std::vector<insn_desc_t> get_instructions() = 0;
15 virtual std::vector<disasm_insn_t*> get_disasms() = 0;
16 virtual const char* name() = 0;
17 virtual void reset() {};
18 virtual void set_debug(bool value) {};
19 virtual ~extension_t();
20
21 void set_processor(processor_t* _p) { p = _p; }
22 protected:
23 processor_t* p;
24
25 void illegal_instruction();
26 void raise_interrupt();
27 void clear_interrupt();
28 };
29
30 std::map<std::string, std::function<extension_t*()>>& extensions();
31
32 #define REGISTER_EXTENSION(name, constructor) \
33 class register_##name { \
34 public: register_##name() { extensions()[#name] = constructor; } \
35 }; static register_##name dummy_##name;
36
37 #endif