f73a5a82d592b70f9b9de9e55fce5dea26e2757e
[riscv-isa-sim.git] / riscv / extension.h
1 #ifndef _RISCV_COPROCESSOR_H
2 #define _RISCV_COPROCESSOR_H
3
4 #include "processor.h"
5 #include "disasm.h"
6 #include <vector>
7 #include <functional>
8
9 class extension_t
10 {
11 public:
12 virtual std::vector<insn_desc_t> get_instructions() = 0;
13 virtual std::vector<disasm_insn_t*> get_disasms() = 0;
14 virtual const char* name() = 0;
15 virtual void reset() {};
16 virtual void set_debug(bool value) {};
17 virtual ~extension_t();
18
19 void set_processor(processor_t* _p) { p = _p; }
20 protected:
21 processor_t* p;
22
23 void illegal_instruction();
24 void raise_interrupt();
25 void clear_interrupt();
26 };
27
28 std::function<extension_t*()> find_extension(const char* name);
29 void register_extension(const char* name, std::function<extension_t*()> f);
30
31 #define REGISTER_EXTENSION(name, constructor) \
32 class register_##name { \
33 public: register_##name() { register_extension(#name, constructor); } \
34 }; static register_##name dummy_##name;
35
36 #endif