aeefb96d0fba943e6d6ea411a81a9776e00fef93
[riscv-isa-sim.git] / riscv / gdbserver.cc
1 #include <arpa/inet.h>
2 #include <errno.h>
3 #include <fcntl.h>
4 #include <stdlib.h>
5 #include <string.h>
6 #include <sys/socket.h>
7 #include <sys/types.h>
8 #include <unistd.h>
9
10 #include <algorithm>
11 #include <cassert>
12 #include <cinttypes>
13 #include <cstdio>
14 #include <vector>
15
16 #include "disasm.h"
17 #include "sim.h"
18 #include "gdbserver.h"
19 #include "mmu.h"
20
21 #define C_EBREAK 0x9002
22 #define EBREAK 0x00100073
23
24 //////////////////////////////////////// Utility Functions
25
26 #undef DEBUG
27 #ifdef DEBUG
28 # define D(x) x
29 #else
30 # define D(x)
31 #endif // DEBUG
32
33 void die(const char* msg)
34 {
35 fprintf(stderr, "gdbserver code died: %s\n", msg);
36 abort();
37 }
38
39 // gdb's register list is defined in riscv_gdb_reg_names gdb/riscv-tdep.c in
40 // its source tree. We must interpret the numbers the same here.
41 enum {
42 REG_XPR0 = 0,
43 REG_XPR31 = 31,
44 REG_PC = 32,
45 REG_FPR0 = 33,
46 REG_FPR31 = 64,
47 REG_CSR0 = 65,
48 REG_CSR4095 = 4160,
49 REG_PRIV = 4161
50 };
51
52 //////////////////////////////////////// Functions to generate RISC-V opcodes.
53
54 // TODO: Does this already exist somewhere?
55
56 #define ZERO 0
57 // Using regnames.cc as source. The RVG Calling Convention of the 2.0 RISC-V
58 // spec says it should be 2 and 3.
59 #define S0 8
60 #define S1 9
61 static uint32_t bits(uint32_t value, unsigned int hi, unsigned int lo) {
62 return (value >> lo) & ((1 << (hi+1-lo)) - 1);
63 }
64
65 static uint32_t bit(uint32_t value, unsigned int b) {
66 return (value >> b) & 1;
67 }
68
69 static uint32_t jal(unsigned int rd, uint32_t imm) {
70 return (bit(imm, 20) << 31) |
71 (bits(imm, 10, 1) << 21) |
72 (bit(imm, 11) << 20) |
73 (bits(imm, 19, 12) << 12) |
74 (rd << 7) |
75 MATCH_JAL;
76 }
77
78 static uint32_t csrsi(unsigned int csr, uint16_t imm) {
79 return (csr << 20) |
80 (bits(imm, 4, 0) << 15) |
81 MATCH_CSRRSI;
82 }
83
84 static uint32_t csrci(unsigned int csr, uint16_t imm) {
85 return (csr << 20) |
86 (bits(imm, 4, 0) << 15) |
87 MATCH_CSRRCI;
88 }
89
90 static uint32_t csrr(unsigned int rd, unsigned int csr) {
91 return (csr << 20) | (rd << 7) | MATCH_CSRRS;
92 }
93
94 static uint32_t csrw(unsigned int source, unsigned int csr) {
95 return (csr << 20) | (source << 15) | MATCH_CSRRW;
96 }
97
98 static uint32_t fence_i()
99 {
100 return MATCH_FENCE_I;
101 }
102
103 static uint32_t sb(unsigned int src, unsigned int base, uint16_t offset)
104 {
105 return (bits(offset, 11, 5) << 25) |
106 (src << 20) |
107 (base << 15) |
108 (bits(offset, 4, 0) << 7) |
109 MATCH_SB;
110 }
111
112 static uint32_t sh(unsigned int src, unsigned int base, uint16_t offset)
113 {
114 return (bits(offset, 11, 5) << 25) |
115 (src << 20) |
116 (base << 15) |
117 (bits(offset, 4, 0) << 7) |
118 MATCH_SH;
119 }
120
121 static uint32_t sw(unsigned int src, unsigned int base, uint16_t offset)
122 {
123 return (bits(offset, 11, 5) << 25) |
124 (src << 20) |
125 (base << 15) |
126 (bits(offset, 4, 0) << 7) |
127 MATCH_SW;
128 }
129
130 static uint32_t sd(unsigned int src, unsigned int base, uint16_t offset)
131 {
132 return (bits(offset, 11, 5) << 25) |
133 (bits(src, 4, 0) << 20) |
134 (base << 15) |
135 (bits(offset, 4, 0) << 7) |
136 MATCH_SD;
137 }
138
139 static uint32_t sq(unsigned int src, unsigned int base, uint16_t offset)
140 {
141 #if 0
142 return (bits(offset, 11, 5) << 25) |
143 (bits(src, 4, 0) << 20) |
144 (base << 15) |
145 (bits(offset, 4, 0) << 7) |
146 MATCH_SQ;
147 #else
148 abort();
149 #endif
150 }
151
152 static uint32_t lq(unsigned int rd, unsigned int base, uint16_t offset)
153 {
154 #if 0
155 return (bits(offset, 11, 0) << 20) |
156 (base << 15) |
157 (bits(rd, 4, 0) << 7) |
158 MATCH_LQ;
159 #else
160 abort();
161 #endif
162 }
163
164 static uint32_t ld(unsigned int rd, unsigned int base, uint16_t offset)
165 {
166 return (bits(offset, 11, 0) << 20) |
167 (base << 15) |
168 (bits(rd, 4, 0) << 7) |
169 MATCH_LD;
170 }
171
172 static uint32_t lw(unsigned int rd, unsigned int base, uint16_t offset)
173 {
174 return (bits(offset, 11, 0) << 20) |
175 (base << 15) |
176 (bits(rd, 4, 0) << 7) |
177 MATCH_LW;
178 }
179
180 static uint32_t lh(unsigned int rd, unsigned int base, uint16_t offset)
181 {
182 return (bits(offset, 11, 0) << 20) |
183 (base << 15) |
184 (bits(rd, 4, 0) << 7) |
185 MATCH_LH;
186 }
187
188 static uint32_t lb(unsigned int rd, unsigned int base, uint16_t offset)
189 {
190 return (bits(offset, 11, 0) << 20) |
191 (base << 15) |
192 (bits(rd, 4, 0) << 7) |
193 MATCH_LB;
194 }
195
196 static uint32_t fsw(unsigned int src, unsigned int base, uint16_t offset)
197 {
198 return (bits(offset, 11, 5) << 25) |
199 (bits(src, 4, 0) << 20) |
200 (base << 15) |
201 (bits(offset, 4, 0) << 7) |
202 MATCH_FSW;
203 }
204
205 static uint32_t fsd(unsigned int src, unsigned int base, uint16_t offset)
206 {
207 return (bits(offset, 11, 5) << 25) |
208 (bits(src, 4, 0) << 20) |
209 (base << 15) |
210 (bits(offset, 4, 0) << 7) |
211 MATCH_FSD;
212 }
213
214 static uint32_t flw(unsigned int src, unsigned int base, uint16_t offset)
215 {
216 return (bits(offset, 11, 5) << 25) |
217 (bits(src, 4, 0) << 20) |
218 (base << 15) |
219 (bits(offset, 4, 0) << 7) |
220 MATCH_FLW;
221 }
222
223 static uint32_t fld(unsigned int src, unsigned int base, uint16_t offset)
224 {
225 return (bits(offset, 11, 5) << 25) |
226 (bits(src, 4, 0) << 20) |
227 (base << 15) |
228 (bits(offset, 4, 0) << 7) |
229 MATCH_FLD;
230 }
231
232 static uint32_t addi(unsigned int dest, unsigned int src, uint16_t imm)
233 {
234 return (bits(imm, 11, 0) << 20) |
235 (src << 15) |
236 (dest << 7) |
237 MATCH_ADDI;
238 }
239
240 static uint32_t ori(unsigned int dest, unsigned int src, uint16_t imm)
241 {
242 return (bits(imm, 11, 0) << 20) |
243 (src << 15) |
244 (dest << 7) |
245 MATCH_ORI;
246 }
247
248 static uint32_t xori(unsigned int dest, unsigned int src, uint16_t imm)
249 {
250 return (bits(imm, 11, 0) << 20) |
251 (src << 15) |
252 (dest << 7) |
253 MATCH_XORI;
254 }
255
256 static uint32_t srli(unsigned int dest, unsigned int src, uint8_t shamt)
257 {
258 return (bits(shamt, 4, 0) << 20) |
259 (src << 15) |
260 (dest << 7) |
261 MATCH_SRLI;
262 }
263
264
265 static uint32_t nop()
266 {
267 return addi(0, 0, 0);
268 }
269
270 template <typename T>
271 unsigned int circular_buffer_t<T>::size() const
272 {
273 if (end >= start)
274 return end - start;
275 else
276 return end + capacity - start;
277 }
278
279 template <typename T>
280 void circular_buffer_t<T>::consume(unsigned int bytes)
281 {
282 start = (start + bytes) % capacity;
283 }
284
285 template <typename T>
286 unsigned int circular_buffer_t<T>::contiguous_empty_size() const
287 {
288 if (end >= start)
289 if (start == 0)
290 return capacity - end - 1;
291 else
292 return capacity - end;
293 else
294 return start - end - 1;
295 }
296
297 template <typename T>
298 unsigned int circular_buffer_t<T>::contiguous_data_size() const
299 {
300 if (end >= start)
301 return end - start;
302 else
303 return capacity - start;
304 }
305
306 template <typename T>
307 void circular_buffer_t<T>::data_added(unsigned int bytes)
308 {
309 end += bytes;
310 assert(end <= capacity);
311 if (end == capacity)
312 end = 0;
313 }
314
315 template <typename T>
316 void circular_buffer_t<T>::reset()
317 {
318 start = 0;
319 end = 0;
320 }
321
322 template <typename T>
323 void circular_buffer_t<T>::append(const T *src, unsigned int count)
324 {
325 unsigned int copy = std::min(count, contiguous_empty_size());
326 memcpy(contiguous_empty(), src, copy * sizeof(T));
327 data_added(copy);
328 count -= copy;
329 if (count > 0) {
330 assert(count < contiguous_empty_size());
331 memcpy(contiguous_empty(), src, count * sizeof(T));
332 data_added(count);
333 }
334 }
335
336 ////////////////////////////// Debug Operations
337
338 class halt_op_t : public operation_t
339 {
340 public:
341 halt_op_t(gdbserver_t& gdbserver, bool send_status=false) :
342 operation_t(gdbserver), send_status(send_status),
343 state(ST_ENTER) {};
344
345 void write_dpc_program() {
346 gs.dr_write32(0, csrsi(CSR_DCSR, DCSR_HALT));
347 gs.dr_write32(1, csrr(S0, CSR_DPC));
348 gs.dr_write_store(2, S0, SLOT_DATA0);
349 gs.dr_write_jump(3);
350 gs.set_interrupt(0);
351 }
352
353 bool perform_step(unsigned int step) {
354 switch (state) {
355 gs.tselect_valid = false;
356 case ST_ENTER:
357 if (gs.xlen == 0) {
358 gs.dr_write32(0, xori(S1, ZERO, -1));
359 gs.dr_write32(1, srli(S1, S1, 31));
360 // 0x00000001 0x00000001:ffffffff 0x00000001:ffffffff:ffffffff:ffffffff
361 gs.dr_write32(2, sw(S1, ZERO, DEBUG_RAM_START));
362 gs.dr_write32(3, srli(S1, S1, 31));
363 // 0x00000000 0x00000000:00000003 0x00000000:00000003:ffffffff:ffffffff
364 gs.dr_write32(4, sw(S1, ZERO, DEBUG_RAM_START + 4));
365 gs.dr_write_jump(5);
366 gs.set_interrupt(0);
367 state = ST_XLEN;
368
369 } else {
370 write_dpc_program();
371 state = ST_DPC;
372 }
373 return false;
374
375 case ST_XLEN:
376 {
377 uint32_t word0 = gs.dr_read32(0);
378 uint32_t word1 = gs.dr_read32(1);
379
380 if (word0 == 1 && word1 == 0) {
381 gs.xlen = 32;
382 } else if (word0 == 0xffffffff && word1 == 3) {
383 gs.xlen = 64;
384 } else if (word0 == 0xffffffff && word1 == 0xffffffff) {
385 gs.xlen = 128;
386 }
387
388 write_dpc_program();
389 state = ST_DPC;
390 return false;
391 }
392
393 case ST_DPC:
394 gs.dpc = gs.dr_read(SLOT_DATA0);
395 gs.dr_write32(0, csrr(S0, CSR_MSTATUS));
396 gs.dr_write_store(1, S0, SLOT_DATA0);
397 gs.dr_write_jump(2);
398 gs.set_interrupt(0);
399 state = ST_MSTATUS;
400 return false;
401
402 case ST_MSTATUS:
403 gs.mstatus = gs.dr_read(SLOT_DATA0);
404 gs.dr_write32(0, csrr(S0, CSR_DCSR));
405 gs.dr_write32(1, sw(S0, 0, (uint16_t) DEBUG_RAM_START + 16));
406 gs.dr_write_jump(2);
407 gs.set_interrupt(0);
408 state = ST_DCSR;
409 return false;
410
411 case ST_DCSR:
412 gs.dcsr = gs.dr_read32(4);
413
414 gs.sptbr_valid = false;
415 gs.pte_cache.clear();
416
417 if (send_status) {
418 switch (get_field(gs.dcsr, DCSR_CAUSE)) {
419 case DCSR_CAUSE_NONE:
420 fprintf(stderr, "Internal error. Processor halted without reason.\n");
421 abort();
422
423 case DCSR_CAUSE_DEBUGINT:
424 gs.send_packet("S02"); // Pretend program received SIGINT.
425 break;
426
427 case DCSR_CAUSE_HWBP:
428 case DCSR_CAUSE_STEP:
429 case DCSR_CAUSE_HALT:
430 // There's no gdb code for this.
431 gs.send_packet("T05");
432 break;
433 case DCSR_CAUSE_SWBP:
434 gs.send_packet("T05swbreak:;");
435 break;
436 }
437 }
438 return true;
439
440 default:
441 assert(0);
442 }
443 }
444
445 private:
446 bool send_status;
447 enum {
448 ST_ENTER,
449 ST_XLEN,
450 ST_DPC,
451 ST_MSTATUS,
452 ST_DCSR
453 } state;
454 };
455
456 class continue_op_t : public operation_t
457 {
458 public:
459 continue_op_t(gdbserver_t& gdbserver, bool single_step) :
460 operation_t(gdbserver), single_step(single_step) {};
461
462 bool perform_step(unsigned int step) {
463 D(fprintf(stderr, "continue step %d\n", step));
464 switch (step) {
465 case 0:
466 gs.dr_write_load(0, S0, SLOT_DATA0);
467 gs.dr_write32(1, csrw(S0, CSR_DPC));
468 // TODO: Isn't there a fence.i in Debug ROM already?
469 if (gs.fence_i_required) {
470 gs.dr_write32(2, fence_i());
471 gs.dr_write_jump(3);
472 gs.fence_i_required = false;
473 } else {
474 gs.dr_write_jump(2);
475 }
476 gs.dr_write(SLOT_DATA0, gs.dpc);
477 gs.set_interrupt(0);
478 return false;
479
480 case 1:
481 gs.dr_write_load(0, S0, SLOT_DATA0);
482 gs.dr_write32(1, csrw(S0, CSR_MSTATUS));
483 gs.dr_write_jump(2);
484 gs.dr_write(SLOT_DATA0, gs.mstatus);
485 gs.set_interrupt(0);
486 return false;
487
488 case 2:
489 gs.dr_write32(0, lw(S0, 0, (uint16_t) DEBUG_RAM_START+16));
490 gs.dr_write32(1, csrw(S0, CSR_DCSR));
491 gs.dr_write_jump(2);
492
493 reg_t dcsr = set_field(gs.dcsr, DCSR_HALT, 0);
494 dcsr = set_field(dcsr, DCSR_STEP, single_step);
495 // Software breakpoints should go here.
496 dcsr = set_field(dcsr, DCSR_EBREAKM, 1);
497 dcsr = set_field(dcsr, DCSR_EBREAKH, 1);
498 dcsr = set_field(dcsr, DCSR_EBREAKS, 1);
499 dcsr = set_field(dcsr, DCSR_EBREAKU, 1);
500 gs.dr_write32(4, dcsr);
501
502 gs.set_interrupt(0);
503 return true;
504 }
505 return false;
506 }
507
508 private:
509 bool single_step;
510 };
511
512 class general_registers_read_op_t : public operation_t
513 {
514 // Register order that gdb expects is:
515 // "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",
516 // "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15",
517 // "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
518 // "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31",
519
520 // Each byte of register data is described by two hex digits. The bytes with
521 // the register are transmitted in target byte order. The size of each
522 // register and their position within the ‘g’ packet are determined by the
523 // gdb internal gdbarch functions DEPRECATED_REGISTER_RAW_SIZE and
524 // gdbarch_register_name.
525
526 public:
527 general_registers_read_op_t(gdbserver_t& gdbserver) :
528 operation_t(gdbserver) {};
529
530 bool perform_step(unsigned int step)
531 {
532 D(fprintf(stderr, "register_read step %d\n", step));
533 if (step == 0) {
534 gs.start_packet();
535
536 // x0 is always zero.
537 if (gs.xlen == 32) {
538 gs.send((uint32_t) 0);
539 } else {
540 gs.send((uint64_t) 0);
541 }
542
543 gs.dr_write_store(0, 1, SLOT_DATA0);
544 gs.dr_write_store(1, 2, SLOT_DATA1);
545 gs.dr_write_jump(2);
546 gs.set_interrupt(0);
547 return false;
548 }
549
550 if (gs.xlen == 32) {
551 gs.send((uint32_t) gs.dr_read(SLOT_DATA0));
552 } else {
553 gs.send((uint64_t) gs.dr_read(SLOT_DATA0));
554 }
555 if (step >= 16) {
556 gs.end_packet();
557 return true;
558 }
559
560 if (gs.xlen == 32) {
561 gs.send((uint32_t) gs.dr_read(SLOT_DATA1));
562 } else {
563 gs.send((uint64_t) gs.dr_read(SLOT_DATA1));
564 }
565
566 unsigned int current_reg = 2 * step + 1;
567 unsigned int i = 0;
568 if (current_reg == S1) {
569 gs.dr_write_load(i++, S1, SLOT_DATA_LAST);
570 }
571 gs.dr_write_store(i++, current_reg, SLOT_DATA0);
572 if (current_reg + 1 == S0) {
573 gs.dr_write32(i++, csrr(S0, CSR_DSCRATCH));
574 }
575 if (step < 15) {
576 gs.dr_write_store(i++, current_reg+1, SLOT_DATA1);
577 }
578 gs.dr_write_jump(i);
579 gs.set_interrupt(0);
580
581 return false;
582 }
583 };
584
585 class register_read_op_t : public operation_t
586 {
587 public:
588 register_read_op_t(gdbserver_t& gdbserver, unsigned int reg) :
589 operation_t(gdbserver), reg(reg) {};
590
591 bool perform_step(unsigned int step)
592 {
593 switch (step) {
594 case 0:
595 if (reg >= REG_XPR0 && reg <= REG_XPR31) {
596 if (gs.xlen == 32) {
597 gs.dr_write32(0, sw(reg - REG_XPR0, 0, (uint16_t) DEBUG_RAM_START + 16));
598 } else {
599 gs.dr_write32(0, sd(reg - REG_XPR0, 0, (uint16_t) DEBUG_RAM_START + 16));
600 }
601 gs.dr_write_jump(1);
602 } else if (reg == REG_PC) {
603 gs.start_packet();
604 if (gs.xlen == 32) {
605 gs.send((uint32_t) gs.dpc);
606 } else {
607 gs.send(gs.dpc);
608 }
609 gs.end_packet();
610 return true;
611 } else if (reg >= REG_FPR0 && reg <= REG_FPR31) {
612 // send(p->state.FPR[reg - REG_FPR0]);
613 if (gs.xlen == 32) {
614 gs.dr_write32(0, fsw(reg - REG_FPR0, 0, (uint16_t) DEBUG_RAM_START + 16));
615 } else {
616 gs.dr_write32(0, fsd(reg - REG_FPR0, 0, (uint16_t) DEBUG_RAM_START + 16));
617 }
618 gs.dr_write_jump(1);
619 } else if (reg >= REG_CSR0 && reg <= REG_CSR4095) {
620 gs.dr_write32(0, csrr(S0, reg - REG_CSR0));
621 gs.dr_write_store(1, S0, SLOT_DATA0);
622 gs.dr_write_jump(2);
623 // If we hit an exception reading the CSR, we'll end up returning ~0 as
624 // the register's value, which is what we want. (Right?)
625 gs.dr_write(SLOT_DATA0, ~(uint64_t) 0);
626 } else if (reg == REG_PRIV) {
627 gs.start_packet();
628 gs.send((uint8_t) get_field(gs.dcsr, DCSR_PRV));
629 gs.end_packet();
630 return true;
631 } else {
632 gs.send_packet("E02");
633 return true;
634 }
635 gs.set_interrupt(0);
636 return false;
637
638 case 1:
639 {
640 unsigned result = gs.dr_read(SLOT_DATA_LAST);
641 if (result) {
642 gs.send_packet("E03");
643 return true;
644 }
645 gs.start_packet();
646 if (gs.xlen == 32) {
647 gs.send(gs.dr_read32(4));
648 } else {
649 gs.send(gs.dr_read(SLOT_DATA0));
650 }
651 gs.end_packet();
652 return true;
653 }
654 }
655 return false;
656 }
657
658 private:
659 unsigned int reg;
660 };
661
662 class register_write_op_t : public operation_t
663 {
664 public:
665 register_write_op_t(gdbserver_t& gdbserver, unsigned int reg, reg_t value) :
666 operation_t(gdbserver), reg(reg), value(value) {};
667
668 bool perform_step(unsigned int step)
669 {
670 gs.dr_write_load(0, S0, SLOT_DATA0);
671 gs.dr_write(SLOT_DATA0, value);
672 if (reg == S0) {
673 gs.dr_write32(1, csrw(S0, CSR_DSCRATCH));
674 gs.dr_write_jump(2);
675 } else if (reg == S1) {
676 gs.dr_write_store(1, S0, SLOT_DATA_LAST);
677 gs.dr_write_jump(2);
678 } else if (reg >= REG_XPR0 && reg <= REG_XPR31) {
679 gs.dr_write32(1, addi(reg, S0, 0));
680 gs.dr_write_jump(2);
681 } else if (reg == REG_PC) {
682 gs.dpc = value;
683 return true;
684 } else if (reg >= REG_FPR0 && reg <= REG_FPR31) {
685 if (gs.xlen == 32) {
686 gs.dr_write32(0, flw(reg - REG_FPR0, 0, (uint16_t) DEBUG_RAM_START + 16));
687 } else {
688 gs.dr_write32(0, fld(reg - REG_FPR0, 0, (uint16_t) DEBUG_RAM_START + 16));
689 }
690 gs.dr_write_jump(1);
691 } else if (reg >= REG_CSR0 && reg <= REG_CSR4095) {
692 gs.dr_write32(1, csrw(S0, reg - REG_CSR0));
693 gs.dr_write_jump(2);
694 if (reg == REG_CSR0 + CSR_SPTBR) {
695 gs.sptbr = value;
696 gs.sptbr_valid = true;
697 }
698 } else if (reg == REG_PRIV) {
699 gs.dcsr = set_field(gs.dcsr, DCSR_PRV, value);
700 return true;
701 } else {
702 gs.send_packet("E02");
703 return true;
704 }
705 gs.set_interrupt(0);
706 gs.send_packet("OK");
707 return true;
708 }
709
710 private:
711 unsigned int reg;
712 reg_t value;
713 };
714
715 class memory_read_op_t : public operation_t
716 {
717 public:
718 // Read length bytes from vaddr, storing the result into data.
719 // If data is NULL, send the result straight to gdb.
720 memory_read_op_t(gdbserver_t& gdbserver, reg_t vaddr, unsigned int length,
721 unsigned char *data=NULL) :
722 operation_t(gdbserver), vaddr(vaddr), length(length), data(data), index(0)
723 {
724 buf = new uint8_t[length];
725 };
726
727 ~memory_read_op_t()
728 {
729 delete[] buf;
730 }
731
732 bool perform_step(unsigned int step)
733 {
734 if (step == 0) {
735 // address goes in S0
736 paddr = gs.translate(vaddr);
737 access_size = gs.find_access_size(paddr, length);
738
739 gs.dr_write_load(0, S0, SLOT_DATA0);
740 switch (access_size) {
741 case 1:
742 gs.dr_write32(1, lb(S1, S0, 0));
743 break;
744 case 2:
745 gs.dr_write32(1, lh(S1, S0, 0));
746 break;
747 case 4:
748 gs.dr_write32(1, lw(S1, S0, 0));
749 break;
750 case 8:
751 gs.dr_write32(1, ld(S1, S0, 0));
752 break;
753 }
754 gs.dr_write_store(2, S1, SLOT_DATA1);
755 gs.dr_write_jump(3);
756 gs.dr_write(SLOT_DATA0, paddr);
757 gs.set_interrupt(0);
758
759 return false;
760 }
761
762 if (gs.dr_read32(DEBUG_RAM_SIZE / 4 - 1)) {
763 // Note that OpenOCD doesn't report this error to gdb by default. They
764 // think it can mess up stack tracing. So far I haven't seen any
765 // problems.
766 gs.send_packet("E99");
767 return true;
768 }
769
770 reg_t value = gs.dr_read(SLOT_DATA1);
771 for (unsigned int i = 0; i < access_size; i++) {
772 if (data) {
773 *(data++) = value & 0xff;
774 D(fprintf(stderr, "%02x", (unsigned int) (value & 0xff)));
775 } else {
776 buf[index++] = value & 0xff;
777 }
778 value >>= 8;
779 }
780 if (data) {
781 D(fprintf(stderr, "\n"));
782 }
783 length -= access_size;
784 paddr += access_size;
785
786 if (length == 0) {
787 if (!data) {
788 gs.start_packet();
789 char buffer[3];
790 for (unsigned int i = 0; i < index; i++) {
791 sprintf(buffer, "%02x", (unsigned int) buf[i]);
792 gs.send(buffer);
793 }
794 gs.end_packet();
795 }
796 return true;
797 } else {
798 gs.dr_write(SLOT_DATA0, paddr);
799 gs.set_interrupt(0);
800 return false;
801 }
802 }
803
804 private:
805 reg_t vaddr;
806 unsigned int length;
807 unsigned char* data;
808 reg_t paddr;
809 unsigned int access_size;
810 unsigned int index;
811 uint8_t *buf;
812 };
813
814 class memory_write_op_t : public operation_t
815 {
816 public:
817 memory_write_op_t(gdbserver_t& gdbserver, reg_t vaddr, unsigned int length,
818 const unsigned char *data) :
819 operation_t(gdbserver), vaddr(vaddr), offset(0), length(length), data(data) {};
820
821 ~memory_write_op_t() {
822 delete[] data;
823 }
824
825 bool perform_step(unsigned int step)
826 {
827 reg_t paddr = gs.translate(vaddr);
828
829 unsigned int data_offset;
830 switch (gs.xlen) {
831 case 32:
832 data_offset = slot_offset32[SLOT_DATA1];
833 break;
834 case 64:
835 data_offset = slot_offset64[SLOT_DATA1];
836 break;
837 case 128:
838 data_offset = slot_offset128[SLOT_DATA1];
839 break;
840 default:
841 abort();
842 }
843
844 if (step == 0) {
845 access_size = gs.find_access_size(paddr, length);
846
847 D(fprintf(stderr, "write to 0x%lx -> 0x%lx (access=%d): ", vaddr, paddr,
848 access_size));
849 for (unsigned int i = 0; i < length; i++) {
850 D(fprintf(stderr, "%02x", data[i]));
851 }
852 D(fprintf(stderr, "\n"));
853
854 // address goes in S0
855 gs.dr_write_load(0, S0, SLOT_DATA0);
856 switch (access_size) {
857 case 1:
858 gs.dr_write32(1, lb(S1, 0, (uint16_t) DEBUG_RAM_START + 4*data_offset));
859 gs.dr_write32(2, sb(S1, S0, 0));
860 gs.dr_write32(data_offset, data[0]);
861 break;
862 case 2:
863 gs.dr_write32(1, lh(S1, 0, (uint16_t) DEBUG_RAM_START + 4*data_offset));
864 gs.dr_write32(2, sh(S1, S0, 0));
865 gs.dr_write32(data_offset, data[0] | (data[1] << 8));
866 break;
867 case 4:
868 gs.dr_write32(1, lw(S1, 0, (uint16_t) DEBUG_RAM_START + 4*data_offset));
869 gs.dr_write32(2, sw(S1, S0, 0));
870 gs.dr_write32(data_offset, data[0] | (data[1] << 8) |
871 (data[2] << 16) | (data[3] << 24));
872 break;
873 case 8:
874 gs.dr_write32(1, ld(S1, 0, (uint16_t) DEBUG_RAM_START + 4*data_offset));
875 gs.dr_write32(2, sd(S1, S0, 0));
876 gs.dr_write32(data_offset, data[0] | (data[1] << 8) |
877 (data[2] << 16) | (data[3] << 24));
878 gs.dr_write32(data_offset+1, data[4] | (data[5] << 8) |
879 (data[6] << 16) | (data[7] << 24));
880 break;
881 default:
882 fprintf(stderr, "gdbserver error: write %d bytes to 0x%016" PRIx64
883 " -> 0x%016" PRIx64 "; access_size=%d\n",
884 length, vaddr, paddr, access_size);
885 gs.send_packet("E12");
886 return true;
887 }
888 gs.dr_write_jump(3);
889 gs.dr_write(SLOT_DATA0, paddr);
890 gs.set_interrupt(0);
891
892 return false;
893 }
894
895 if (gs.dr_read32(DEBUG_RAM_SIZE / 4 - 1)) {
896 gs.send_packet("E98");
897 return true;
898 }
899
900 offset += access_size;
901 if (offset >= length) {
902 gs.send_packet("OK");
903 return true;
904 } else {
905 const unsigned char *d = data + offset;
906 switch (access_size) {
907 case 1:
908 gs.dr_write32(data_offset, d[0]);
909 break;
910 case 2:
911 gs.dr_write32(data_offset, d[0] | (d[1] << 8));
912 break;
913 case 4:
914 gs.dr_write32(data_offset, d[0] | (d[1] << 8) |
915 (d[2] << 16) | (d[3] << 24));
916 break;
917 case 8:
918 gs.dr_write32(data_offset, d[0] | (d[1] << 8) |
919 (d[2] << 16) | (d[3] << 24));
920 gs.dr_write32(data_offset+1, d[4] | (d[5] << 8) |
921 (d[6] << 16) | (d[7] << 24));
922 break;
923 default:
924 gs.send_packet("E13");
925 return true;
926 }
927 gs.dr_write(SLOT_DATA0, paddr + offset);
928 gs.set_interrupt(0);
929 return false;
930 }
931 }
932
933 private:
934 reg_t vaddr;
935 unsigned int offset;
936 unsigned int length;
937 unsigned int access_size;
938 const unsigned char *data;
939 };
940
941 class collect_translation_info_op_t : public operation_t
942 {
943 public:
944 // Read sufficient information from the target into gdbserver structures so
945 // that it's possible to translate vaddr, vaddr+length, and all addresses
946 // in between to physical addresses.
947 collect_translation_info_op_t(gdbserver_t& gdbserver, reg_t vaddr, size_t length) :
948 operation_t(gdbserver), state(STATE_START), vaddr(vaddr), length(length) {};
949
950 bool perform_step(unsigned int step)
951 {
952 unsigned int vm = gs.virtual_memory();
953
954 if (step == 0) {
955 switch (vm) {
956 case VM_MBARE:
957 // Nothing to be done.
958 return true;
959
960 case VM_SV32:
961 levels = 2;
962 ptidxbits = 10;
963 ptesize = 4;
964 break;
965 case VM_SV39:
966 levels = 3;
967 ptidxbits = 9;
968 ptesize = 8;
969 break;
970 case VM_SV48:
971 levels = 4;
972 ptidxbits = 9;
973 ptesize = 8;
974 break;
975
976 default:
977 {
978 char buf[100];
979 sprintf(buf, "VM mode %d is not supported by gdbserver.cc.", vm);
980 die(buf);
981 return true; // die doesn't return, but gcc doesn't know that.
982 }
983 }
984 }
985
986 // Perform any reads from the just-completed action.
987 switch (state) {
988 case STATE_START:
989 break;
990 case STATE_READ_SPTBR:
991 gs.sptbr = gs.dr_read(SLOT_DATA0);
992 gs.sptbr_valid = true;
993 break;
994 case STATE_READ_PTE:
995 if (ptesize == 4) {
996 gs.pte_cache[pte_addr] = gs.dr_read32(4);
997 } else {
998 gs.pte_cache[pte_addr] = ((uint64_t) gs.dr_read32(5) << 32) |
999 gs.dr_read32(4);
1000 }
1001 D(fprintf(stderr, "pte_cache[0x%lx] = 0x%lx\n", pte_addr, gs.pte_cache[pte_addr]));
1002 break;
1003 }
1004
1005 // Set up the next action.
1006 // We only get here for VM_SV32/39/38.
1007
1008 if (!gs.sptbr_valid) {
1009 state = STATE_READ_SPTBR;
1010 gs.dr_write32(0, csrr(S0, CSR_SPTBR));
1011 gs.dr_write_store(1, S0, SLOT_DATA0);
1012 gs.dr_write_jump(2);
1013 gs.set_interrupt(0);
1014 return false;
1015 }
1016
1017 reg_t base = gs.sptbr << PGSHIFT;
1018 int ptshift = (levels - 1) * ptidxbits;
1019 for (unsigned int i = 0; i < levels; i++, ptshift -= ptidxbits) {
1020 reg_t idx = (vaddr >> (PGSHIFT + ptshift)) & ((1 << ptidxbits) - 1);
1021
1022 pte_addr = base + idx * ptesize;
1023 auto it = gs.pte_cache.find(pte_addr);
1024 if (it == gs.pte_cache.end()) {
1025 state = STATE_READ_PTE;
1026 if (ptesize == 4) {
1027 gs.dr_write32(0, lw(S0, 0, (uint16_t) DEBUG_RAM_START + 16));
1028 gs.dr_write32(1, lw(S1, S0, 0));
1029 gs.dr_write32(2, sw(S1, 0, (uint16_t) DEBUG_RAM_START + 16));
1030 } else {
1031 assert(gs.xlen >= 64);
1032 gs.dr_write32(0, ld(S0, 0, (uint16_t) DEBUG_RAM_START + 16));
1033 gs.dr_write32(1, ld(S1, S0, 0));
1034 gs.dr_write32(2, sd(S1, 0, (uint16_t) DEBUG_RAM_START + 16));
1035 }
1036 gs.dr_write32(3, jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*3))));
1037 gs.dr_write32(4, pte_addr);
1038 gs.dr_write32(5, pte_addr >> 32);
1039 gs.set_interrupt(0);
1040 return false;
1041 }
1042
1043 reg_t pte = gs.pte_cache[pte_addr];
1044 reg_t ppn = pte >> PTE_PPN_SHIFT;
1045
1046 if (PTE_TABLE(pte)) { // next level of page table
1047 base = ppn << PGSHIFT;
1048 } else {
1049 // We've collected all the data required for the translation.
1050 return true;
1051 }
1052 }
1053 fprintf(stderr,
1054 "ERROR: gdbserver couldn't find appropriate PTEs to translate 0x%016" PRIx64 "\n",
1055 vaddr);
1056 return true;
1057 }
1058
1059 private:
1060 enum {
1061 STATE_START,
1062 STATE_READ_SPTBR,
1063 STATE_READ_PTE
1064 } state;
1065 reg_t vaddr;
1066 size_t length;
1067 unsigned int levels;
1068 unsigned int ptidxbits;
1069 unsigned int ptesize;
1070 reg_t pte_addr;
1071 };
1072
1073 class hardware_breakpoint_insert_op_t : public operation_t
1074 {
1075 public:
1076 hardware_breakpoint_insert_op_t(gdbserver_t& gdbserver,
1077 hardware_breakpoint_t bp) :
1078 operation_t(gdbserver), state(STATE_START), bp(bp) {};
1079
1080 void write_new_index_program()
1081 {
1082 gs.dr_write_load(0, S0, SLOT_DATA1);
1083 gs.dr_write32(1, csrw(S0, CSR_TSELECT));
1084 gs.dr_write32(2, csrr(S0, CSR_TSELECT));
1085 gs.dr_write_store(3, S0, SLOT_DATA1);
1086 gs.dr_write_jump(4);
1087 gs.dr_write(SLOT_DATA1, bp.index);
1088 }
1089
1090 bool perform_step(unsigned int step)
1091 {
1092 switch (state) {
1093 case STATE_START:
1094 bp.index = 0;
1095 write_new_index_program();
1096 state = STATE_CHECK_INDEX;
1097 break;
1098
1099 case STATE_CHECK_INDEX:
1100 if (gs.dr_read(SLOT_DATA1) != bp.index) {
1101 // We've exhausted breakpoints without finding an appropriate one.
1102 gs.send_packet("E58");
1103 return true;
1104 }
1105
1106 gs.dr_write32(0, csrr(S0, CSR_TDATA1));
1107 gs.dr_write_store(1, S0, SLOT_DATA0);
1108 gs.dr_write_jump(2);
1109 state = STATE_CHECK_MCONTROL;
1110 break;
1111
1112 case STATE_CHECK_MCONTROL:
1113 {
1114 reg_t mcontrol = gs.dr_read(SLOT_DATA0);
1115 unsigned int type = mcontrol >> (gs.xlen - 4);
1116 if (type == 0) {
1117 // We've exhausted breakpoints without finding an appropriate one.
1118 gs.send_packet("E58");
1119 return true;
1120 }
1121
1122 if (type == 2 &&
1123 !get_field(mcontrol, MCONTROL_EXECUTE) &&
1124 !get_field(mcontrol, MCONTROL_LOAD) &&
1125 !get_field(mcontrol, MCONTROL_STORE)) {
1126 // Found an unused trigger.
1127 gs.dr_write_load(0, S0, SLOT_DATA1);
1128 gs.dr_write32(1, csrw(S0, CSR_TDATA1));
1129 gs.dr_write_jump(2);
1130 mcontrol = set_field(0, MCONTROL_ACTION, MCONTROL_ACTION_DEBUG_MODE);
1131 mcontrol = set_field(mcontrol, MCONTROL_DMODE(gs.xlen), 1);
1132 mcontrol = set_field(mcontrol, MCONTROL_MATCH, MCONTROL_MATCH_EQUAL);
1133 mcontrol = set_field(mcontrol, MCONTROL_M, 1);
1134 mcontrol = set_field(mcontrol, MCONTROL_H, 1);
1135 mcontrol = set_field(mcontrol, MCONTROL_S, 1);
1136 mcontrol = set_field(mcontrol, MCONTROL_U, 1);
1137 mcontrol = set_field(mcontrol, MCONTROL_EXECUTE, bp.execute);
1138 mcontrol = set_field(mcontrol, MCONTROL_LOAD, bp.load);
1139 mcontrol = set_field(mcontrol, MCONTROL_STORE, bp.store);
1140 // For store triggers it's nicer to fire just before the
1141 // instruction than just after. However, gdb doesn't clear the
1142 // breakpoints and step before resuming from a store trigger.
1143 // That means that without extra code, you'll keep hitting the
1144 // same watchpoint over and over again. That's not useful at all.
1145 // Instead of fixing this the right way, just set timing=1 for
1146 // those triggers.
1147 if (bp.load || bp.store)
1148 mcontrol = set_field(mcontrol, MCONTROL_TIMING, 1);
1149
1150 gs.dr_write(SLOT_DATA1, mcontrol);
1151 state = STATE_WRITE_ADDRESS;
1152 } else {
1153 bp.index++;
1154 write_new_index_program();
1155 state = STATE_CHECK_INDEX;
1156 }
1157 }
1158 break;
1159
1160 case STATE_WRITE_ADDRESS:
1161 {
1162 gs.dr_write_load(0, S0, SLOT_DATA1);
1163 gs.dr_write32(1, csrw(S0, CSR_TDATA2));
1164 gs.dr_write_jump(2);
1165 gs.dr_write(SLOT_DATA1, bp.vaddr);
1166 gs.set_interrupt(0);
1167 gs.send_packet("OK");
1168
1169 gs.hardware_breakpoints.insert(bp);
1170
1171 return true;
1172 }
1173 }
1174
1175 gs.set_interrupt(0);
1176 return false;
1177 }
1178
1179 private:
1180 enum {
1181 STATE_START,
1182 STATE_CHECK_INDEX,
1183 STATE_CHECK_MCONTROL,
1184 STATE_WRITE_ADDRESS
1185 } state;
1186 hardware_breakpoint_t bp;
1187 };
1188
1189 class maybe_save_tselect_op_t : public operation_t
1190 {
1191 public:
1192 maybe_save_tselect_op_t(gdbserver_t& gdbserver) : operation_t(gdbserver) {};
1193 bool perform_step(unsigned int step) {
1194 if (gs.tselect_valid)
1195 return true;
1196
1197 switch (step) {
1198 case 0:
1199 gs.dr_write32(0, csrr(S0, CSR_TDATA1));
1200 gs.dr_write_store(1, S0, SLOT_DATA0);
1201 gs.dr_write_jump(2);
1202 gs.set_interrupt(0);
1203 return false;
1204 case 1:
1205 gs.tselect = gs.dr_read(SLOT_DATA0);
1206 gs.tselect_valid = true;
1207 break;
1208 }
1209 return true;
1210 }
1211 };
1212
1213 class maybe_restore_tselect_op_t : public operation_t
1214 {
1215 public:
1216 maybe_restore_tselect_op_t(gdbserver_t& gdbserver) : operation_t(gdbserver) {};
1217 bool perform_step(unsigned int step) {
1218 if (gs.tselect_valid) {
1219 gs.dr_write_load(0, S0, SLOT_DATA1);
1220 gs.dr_write32(1, csrw(S0, CSR_TSELECT));
1221 gs.dr_write_jump(2);
1222 gs.dr_write(SLOT_DATA1, gs.tselect);
1223 }
1224 return true;
1225 }
1226 };
1227
1228 class hardware_breakpoint_remove_op_t : public operation_t
1229 {
1230 public:
1231 hardware_breakpoint_remove_op_t(gdbserver_t& gdbserver,
1232 hardware_breakpoint_t bp) :
1233 operation_t(gdbserver), bp(bp) {};
1234
1235 bool perform_step(unsigned int step) {
1236 gs.dr_write32(0, addi(S0, ZERO, bp.index));
1237 gs.dr_write32(1, csrw(S0, CSR_TSELECT));
1238 gs.dr_write32(2, csrw(ZERO, CSR_TDATA1));
1239 gs.dr_write_jump(3);
1240 gs.set_interrupt(0);
1241 return true;
1242 }
1243
1244 private:
1245 hardware_breakpoint_t bp;
1246 };
1247
1248 ////////////////////////////// gdbserver itself
1249
1250 gdbserver_t::gdbserver_t(uint16_t port, sim_t *sim) :
1251 xlen(0),
1252 sim(sim),
1253 client_fd(0),
1254 // gdb likes to send 0x100000 bytes at once when downloading.
1255 recv_buf(0x180000), send_buf(64 * 1024)
1256 {
1257 socket_fd = socket(AF_INET, SOCK_STREAM, 0);
1258 if (socket_fd == -1) {
1259 fprintf(stderr, "failed to make socket: %s (%d)\n", strerror(errno), errno);
1260 abort();
1261 }
1262
1263 fcntl(socket_fd, F_SETFL, O_NONBLOCK);
1264 int reuseaddr = 1;
1265 if (setsockopt(socket_fd, SOL_SOCKET, SO_REUSEADDR, &reuseaddr,
1266 sizeof(int)) == -1) {
1267 fprintf(stderr, "failed setsockopt: %s (%d)\n", strerror(errno), errno);
1268 abort();
1269 }
1270
1271 struct sockaddr_in addr;
1272 memset(&addr, 0, sizeof(addr));
1273 addr.sin_family = AF_INET;
1274 addr.sin_addr.s_addr = INADDR_ANY;
1275 addr.sin_port = htons(port);
1276
1277 if (bind(socket_fd, (struct sockaddr *) &addr, sizeof(addr)) == -1) {
1278 fprintf(stderr, "failed to bind socket: %s (%d)\n", strerror(errno), errno);
1279 abort();
1280 }
1281
1282 if (listen(socket_fd, 1) == -1) {
1283 fprintf(stderr, "failed to listen on socket: %s (%d)\n", strerror(errno), errno);
1284 abort();
1285 }
1286 }
1287
1288 unsigned int gdbserver_t::find_access_size(reg_t address, int length)
1289 {
1290 reg_t composite = address | length;
1291 if ((composite & 0x7) == 0 && xlen >= 64)
1292 return 8;
1293 if ((composite & 0x3) == 0)
1294 return 4;
1295 return 1;
1296 }
1297
1298 reg_t gdbserver_t::translate(reg_t vaddr)
1299 {
1300 unsigned int vm = virtual_memory();
1301 unsigned int levels, ptidxbits, ptesize;
1302
1303 switch (vm) {
1304 case VM_MBARE:
1305 return vaddr;
1306
1307 case VM_SV32:
1308 levels = 2;
1309 ptidxbits = 10;
1310 ptesize = 4;
1311 break;
1312 case VM_SV39:
1313 levels = 3;
1314 ptidxbits = 9;
1315 ptesize = 8;
1316 break;
1317 case VM_SV48:
1318 levels = 4;
1319 ptidxbits = 9;
1320 ptesize = 8;
1321 break;
1322
1323 default:
1324 {
1325 char buf[100];
1326 sprintf(buf, "VM mode %d is not supported by gdbserver.cc.", vm);
1327 die(buf);
1328 return true; // die doesn't return, but gcc doesn't know that.
1329 }
1330 }
1331
1332 // Handle page tables here. There's a bunch of duplicated code with
1333 // collect_translation_info_op_t. :-(
1334 reg_t base = sptbr << PGSHIFT;
1335 int ptshift = (levels - 1) * ptidxbits;
1336 for (unsigned int i = 0; i < levels; i++, ptshift -= ptidxbits) {
1337 reg_t idx = (vaddr >> (PGSHIFT + ptshift)) & ((1 << ptidxbits) - 1);
1338
1339 reg_t pte_addr = base + idx * ptesize;
1340 auto it = pte_cache.find(pte_addr);
1341 if (it == pte_cache.end()) {
1342 fprintf(stderr, "ERROR: gdbserver tried to translate 0x%016" PRIx64
1343 " without first collecting the relevant PTEs.\n", vaddr);
1344 die("gdbserver_t::translate()");
1345 }
1346
1347 reg_t pte = pte_cache[pte_addr];
1348 reg_t ppn = pte >> PTE_PPN_SHIFT;
1349
1350 if (PTE_TABLE(pte)) { // next level of page table
1351 base = ppn << PGSHIFT;
1352 } else {
1353 // We've collected all the data required for the translation.
1354 reg_t vpn = vaddr >> PGSHIFT;
1355 reg_t paddr = (ppn | (vpn & ((reg_t(1) << ptshift) - 1))) << PGSHIFT;
1356 paddr += vaddr & (PGSIZE-1);
1357 D(fprintf(stderr, "gdbserver translate 0x%lx -> 0x%lx\n", vaddr, paddr));
1358 return paddr;
1359 }
1360 }
1361
1362 fprintf(stderr, "ERROR: gdbserver tried to translate 0x%016" PRIx64
1363 " but the relevant PTEs are invalid.\n", vaddr);
1364 // TODO: Is it better to throw an exception here?
1365 return -1;
1366 }
1367
1368 unsigned int gdbserver_t::privilege_mode()
1369 {
1370 unsigned int mode = get_field(dcsr, DCSR_PRV);
1371 if (get_field(mstatus, MSTATUS_MPRV))
1372 mode = get_field(mstatus, MSTATUS_MPP);
1373 return mode;
1374 }
1375
1376 unsigned int gdbserver_t::virtual_memory()
1377 {
1378 unsigned int mode = privilege_mode();
1379 if (mode == PRV_M)
1380 return VM_MBARE;
1381 return get_field(mstatus, MSTATUS_VM);
1382 }
1383
1384 void gdbserver_t::dr_write32(unsigned int index, uint32_t value)
1385 {
1386 sim->debug_module.ram_write32(index, value);
1387 }
1388
1389 void gdbserver_t::dr_write64(unsigned int index, uint64_t value)
1390 {
1391 dr_write32(index, value);
1392 dr_write32(index+1, value >> 32);
1393 }
1394
1395 void gdbserver_t::dr_write(enum slot slot, uint64_t value)
1396 {
1397 switch (xlen) {
1398 case 32:
1399 dr_write32(slot_offset32[slot], value);
1400 break;
1401 case 64:
1402 dr_write64(slot_offset64[slot], value);
1403 break;
1404 case 128:
1405 default:
1406 abort();
1407 }
1408 }
1409
1410 void gdbserver_t::dr_write_jump(unsigned int index)
1411 {
1412 dr_write32(index, jal(0,
1413 (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*index))));
1414 }
1415
1416 void gdbserver_t::dr_write_store(unsigned int index, unsigned int reg, enum slot slot)
1417 {
1418 assert(slot != SLOT_INST0 || index > 2);
1419 assert(slot != SLOT_DATA0 || index < 4 || index > 6);
1420 assert(slot != SLOT_DATA1 || index < 5 || index > 10);
1421 assert(slot != SLOT_DATA_LAST || index < 6 || index > 14);
1422 switch (xlen) {
1423 case 32:
1424 return dr_write32(index,
1425 sw(reg, 0, (uint16_t) DEBUG_RAM_START + 4 * slot_offset32[slot]));
1426 case 64:
1427 return dr_write32(index,
1428 sd(reg, 0, (uint16_t) DEBUG_RAM_START + 4 * slot_offset64[slot]));
1429 case 128:
1430 return dr_write32(index,
1431 sq(reg, 0, (uint16_t) DEBUG_RAM_START + 4 * slot_offset128[slot]));
1432 default:
1433 fprintf(stderr, "xlen is %d!\n", xlen);
1434 abort();
1435 }
1436 }
1437
1438 void gdbserver_t::dr_write_load(unsigned int index, unsigned int reg, enum slot slot)
1439 {
1440 switch (xlen) {
1441 case 32:
1442 return dr_write32(index,
1443 lw(reg, 0, (uint16_t) DEBUG_RAM_START + 4 * slot_offset32[slot]));
1444 case 64:
1445 return dr_write32(index,
1446 ld(reg, 0, (uint16_t) DEBUG_RAM_START + 4 * slot_offset64[slot]));
1447 case 128:
1448 return dr_write32(index,
1449 lq(reg, 0, (uint16_t) DEBUG_RAM_START + 4 * slot_offset128[slot]));
1450 default:
1451 fprintf(stderr, "xlen is %d!\n", xlen);
1452 abort();
1453 }
1454 }
1455
1456 uint32_t gdbserver_t::dr_read32(unsigned int index)
1457 {
1458 uint32_t value = sim->debug_module.ram_read32(index);
1459 D(fprintf(stderr, "read32(%d) -> 0x%x\n", index, value));
1460 return value;
1461 }
1462
1463 uint64_t gdbserver_t::dr_read64(unsigned int index)
1464 {
1465 return ((uint64_t) dr_read32(index+1) << 32) | dr_read32(index);
1466 }
1467
1468 uint64_t gdbserver_t::dr_read(enum slot slot)
1469 {
1470 switch (xlen) {
1471 case 32:
1472 return dr_read32(slot_offset32[slot]);
1473 case 64:
1474 return dr_read64(slot_offset64[slot]);
1475 case 128:
1476 abort();
1477 default:
1478 abort();
1479 }
1480 }
1481
1482 void gdbserver_t::add_operation(operation_t* operation)
1483 {
1484 operation_queue.push(operation);
1485 }
1486
1487 void gdbserver_t::accept()
1488 {
1489 client_fd = ::accept(socket_fd, NULL, NULL);
1490 if (client_fd == -1) {
1491 if (errno == EAGAIN) {
1492 // No client waiting to connect right now.
1493 } else {
1494 fprintf(stderr, "failed to accept on socket: %s (%d)\n", strerror(errno),
1495 errno);
1496 abort();
1497 }
1498 } else {
1499 fcntl(client_fd, F_SETFL, O_NONBLOCK);
1500
1501 expect_ack = false;
1502 extended_mode = false;
1503
1504 // gdb wants the core to be halted when it attaches.
1505 add_operation(new halt_op_t(*this));
1506 }
1507 }
1508
1509 void gdbserver_t::read()
1510 {
1511 // Reading from a non-blocking socket still blocks if there is no data
1512 // available.
1513
1514 size_t count = recv_buf.contiguous_empty_size();
1515 ssize_t bytes = ::read(client_fd, recv_buf.contiguous_empty(), count);
1516 if (bytes == -1) {
1517 if (errno == EAGAIN) {
1518 // We'll try again the next call.
1519 } else {
1520 fprintf(stderr, "failed to read on socket: %s (%d)\n", strerror(errno), errno);
1521 abort();
1522 }
1523 } else if (bytes == 0) {
1524 // The remote disconnected.
1525 client_fd = 0;
1526 processor_t *p = sim->get_core(0);
1527 // TODO p->set_halted(false, HR_NONE);
1528 recv_buf.reset();
1529 send_buf.reset();
1530 } else {
1531 recv_buf.data_added(bytes);
1532 }
1533 }
1534
1535 void gdbserver_t::write()
1536 {
1537 if (send_buf.empty())
1538 return;
1539
1540 while (!send_buf.empty()) {
1541 unsigned int count = send_buf.contiguous_data_size();
1542 assert(count > 0);
1543 ssize_t bytes = ::write(client_fd, send_buf.contiguous_data(), count);
1544 if (bytes == -1) {
1545 fprintf(stderr, "failed to write to socket: %s (%d)\n", strerror(errno), errno);
1546 abort();
1547 } else if (bytes == 0) {
1548 // Client can't take any more data right now.
1549 break;
1550 } else {
1551 D(fprintf(stderr, "wrote %ld bytes: ", bytes));
1552 for (unsigned int i = 0; i < bytes; i++) {
1553 D(fprintf(stderr, "%c", send_buf[i]));
1554 }
1555 D(fprintf(stderr, "\n"));
1556 send_buf.consume(bytes);
1557 }
1558 }
1559 }
1560
1561 void print_packet(const std::vector<uint8_t> &packet)
1562 {
1563 for (uint8_t c : packet) {
1564 if (c >= ' ' and c <= '~')
1565 fprintf(stderr, "%c", c);
1566 else
1567 fprintf(stderr, "\\x%02x", c);
1568 }
1569 fprintf(stderr, "\n");
1570 }
1571
1572 uint8_t compute_checksum(const std::vector<uint8_t> &packet)
1573 {
1574 uint8_t checksum = 0;
1575 for (auto i = packet.begin() + 1; i != packet.end() - 3; i++ ) {
1576 checksum += *i;
1577 }
1578 return checksum;
1579 }
1580
1581 uint8_t character_hex_value(uint8_t character)
1582 {
1583 if (character >= '0' && character <= '9')
1584 return character - '0';
1585 if (character >= 'a' && character <= 'f')
1586 return 10 + character - 'a';
1587 if (character >= 'A' && character <= 'F')
1588 return 10 + character - 'A';
1589 return 0xff;
1590 }
1591
1592 uint8_t extract_checksum(const std::vector<uint8_t> &packet)
1593 {
1594 return character_hex_value(*(packet.end() - 1)) +
1595 16 * character_hex_value(*(packet.end() - 2));
1596 }
1597
1598 void gdbserver_t::process_requests()
1599 {
1600 // See https://sourceware.org/gdb/onlinedocs/gdb/Remote-Protocol.html
1601
1602 while (!recv_buf.empty()) {
1603 std::vector<uint8_t> packet;
1604 for (unsigned int i = 0; i < recv_buf.size(); i++) {
1605 uint8_t b = recv_buf[i];
1606
1607 if (packet.empty() && expect_ack && b == '+') {
1608 recv_buf.consume(1);
1609 break;
1610 }
1611
1612 if (packet.empty() && b == 3) {
1613 D(fprintf(stderr, "Received interrupt\n"));
1614 recv_buf.consume(1);
1615 handle_interrupt();
1616 break;
1617 }
1618
1619 if (b == '$') {
1620 // Start of new packet.
1621 if (!packet.empty()) {
1622 fprintf(stderr, "Received malformed %ld-byte packet from debug client: ",
1623 packet.size());
1624 print_packet(packet);
1625 recv_buf.consume(i);
1626 break;
1627 }
1628 }
1629
1630 packet.push_back(b);
1631
1632 // Packets consist of $<packet-data>#<checksum>
1633 // where <checksum> is
1634 if (packet.size() >= 4 &&
1635 packet[packet.size()-3] == '#') {
1636 handle_packet(packet);
1637 recv_buf.consume(i+1);
1638 break;
1639 }
1640 }
1641 // There's a partial packet in the buffer. Wait until we get more data to
1642 // process it.
1643 if (packet.size()) {
1644 break;
1645 }
1646 }
1647
1648 if (recv_buf.full()) {
1649 fprintf(stderr,
1650 "Receive buffer is full, but no complete packet was found!\n");
1651 for (unsigned line = 0; line < 8; line++) {
1652 for (unsigned i = 0; i < 16; i++) {
1653 fprintf(stderr, "%02x ", recv_buf.entry(line * 16 + i));
1654 }
1655 for (unsigned i = 0; i < 16; i++) {
1656 uint8_t e = recv_buf.entry(line * 16 + i);
1657 if (e >= ' ' && e <= '~')
1658 fprintf(stderr, "%c", e);
1659 else
1660 fprintf(stderr, ".");
1661 }
1662 fprintf(stderr, "\n");
1663 }
1664 assert(!recv_buf.full());
1665 }
1666 }
1667
1668 void gdbserver_t::handle_halt_reason(const std::vector<uint8_t> &packet)
1669 {
1670 send_packet("S00");
1671 }
1672
1673 void gdbserver_t::handle_general_registers_read(const std::vector<uint8_t> &packet)
1674 {
1675 add_operation(new general_registers_read_op_t(*this));
1676 }
1677
1678 void gdbserver_t::set_interrupt(uint32_t hartid) {
1679 sim->debug_module.set_interrupt(hartid);
1680 }
1681
1682 // First byte is the most-significant one.
1683 // Eg. "08675309" becomes 0x08675309.
1684 uint64_t consume_hex_number(std::vector<uint8_t>::const_iterator &iter,
1685 std::vector<uint8_t>::const_iterator end)
1686 {
1687 uint64_t value = 0;
1688
1689 while (iter != end) {
1690 uint8_t c = *iter;
1691 uint64_t c_value = character_hex_value(c);
1692 if (c_value > 15)
1693 break;
1694 iter++;
1695 value <<= 4;
1696 value += c_value;
1697 }
1698 return value;
1699 }
1700
1701 // First byte is the least-significant one.
1702 // Eg. "08675309" becomes 0x09536708
1703 uint64_t gdbserver_t::consume_hex_number_le(
1704 std::vector<uint8_t>::const_iterator &iter,
1705 std::vector<uint8_t>::const_iterator end)
1706 {
1707 uint64_t value = 0;
1708 unsigned int shift = 4;
1709
1710 while (iter != end) {
1711 uint8_t c = *iter;
1712 uint64_t c_value = character_hex_value(c);
1713 if (c_value > 15)
1714 break;
1715 iter++;
1716 value |= c_value << shift;
1717 if ((shift % 8) == 0)
1718 shift += 12;
1719 else
1720 shift -= 4;
1721 }
1722 if (shift > (xlen+4)) {
1723 fprintf(stderr,
1724 "gdb sent too many data bytes. That means it thinks XLEN is greater "
1725 "than %d.\nTo fix that, tell gdb: set arch riscv:rv%d\n",
1726 xlen, xlen);
1727 }
1728 return value;
1729 }
1730
1731 void consume_string(std::string &str, std::vector<uint8_t>::const_iterator &iter,
1732 std::vector<uint8_t>::const_iterator end, uint8_t separator)
1733 {
1734 while (iter != end && *iter != separator) {
1735 str.append(1, (char) *iter);
1736 iter++;
1737 }
1738 }
1739
1740 void gdbserver_t::handle_register_read(const std::vector<uint8_t> &packet)
1741 {
1742 // p n
1743
1744 std::vector<uint8_t>::const_iterator iter = packet.begin() + 2;
1745 unsigned int n = consume_hex_number(iter, packet.end());
1746 if (*iter != '#')
1747 return send_packet("E01");
1748
1749 add_operation(new register_read_op_t(*this, n));
1750 }
1751
1752 void gdbserver_t::handle_register_write(const std::vector<uint8_t> &packet)
1753 {
1754 // P n...=r...
1755
1756 std::vector<uint8_t>::const_iterator iter = packet.begin() + 2;
1757 unsigned int n = consume_hex_number(iter, packet.end());
1758 if (*iter != '=')
1759 return send_packet("E05");
1760 iter++;
1761
1762 reg_t value = consume_hex_number_le(iter, packet.end());
1763 if (*iter != '#')
1764 return send_packet("E06");
1765
1766 processor_t *p = sim->get_core(0);
1767
1768 add_operation(new register_write_op_t(*this, n, value));
1769
1770 return send_packet("OK");
1771 }
1772
1773 void gdbserver_t::handle_memory_read(const std::vector<uint8_t> &packet)
1774 {
1775 // m addr,length
1776 std::vector<uint8_t>::const_iterator iter = packet.begin() + 2;
1777 reg_t address = consume_hex_number(iter, packet.end());
1778 if (*iter != ',')
1779 return send_packet("E10");
1780 iter++;
1781 reg_t length = consume_hex_number(iter, packet.end());
1782 if (*iter != '#')
1783 return send_packet("E11");
1784
1785 add_operation(new collect_translation_info_op_t(*this, address, length));
1786 add_operation(new memory_read_op_t(*this, address, length));
1787 }
1788
1789 void gdbserver_t::handle_memory_binary_write(const std::vector<uint8_t> &packet)
1790 {
1791 // X addr,length:XX...
1792 std::vector<uint8_t>::const_iterator iter = packet.begin() + 2;
1793 reg_t address = consume_hex_number(iter, packet.end());
1794 if (*iter != ',')
1795 return send_packet("E20");
1796 iter++;
1797 reg_t length = consume_hex_number(iter, packet.end());
1798 if (*iter != ':')
1799 return send_packet("E21");
1800 iter++;
1801
1802 if (length == 0) {
1803 return send_packet("OK");
1804 }
1805
1806 unsigned char *data = new unsigned char[length];
1807 for (unsigned int i = 0; i < length; i++) {
1808 if (iter == packet.end()) {
1809 return send_packet("E22");
1810 }
1811 uint8_t c = *iter;
1812 iter++;
1813 if (c == '}') {
1814 // The binary data representation uses 7d (ascii ‘}’) as an escape
1815 // character. Any escaped byte is transmitted as the escape character
1816 // followed by the original character XORed with 0x20. For example, the
1817 // byte 0x7d would be transmitted as the two bytes 0x7d 0x5d. The bytes
1818 // 0x23 (ascii ‘#’), 0x24 (ascii ‘$’), and 0x7d (ascii ‘}’) must always
1819 // be escaped.
1820 if (iter == packet.end()) {
1821 return send_packet("E23");
1822 }
1823 c = (*iter) ^ 0x20;
1824 iter++;
1825 }
1826 data[i] = c;
1827 }
1828 if (*iter != '#')
1829 return send_packet("E4b"); // EOVERFLOW
1830
1831 add_operation(new collect_translation_info_op_t(*this, address, length));
1832 add_operation(new memory_write_op_t(*this, address, length, data));
1833 }
1834
1835 void gdbserver_t::handle_continue(const std::vector<uint8_t> &packet)
1836 {
1837 // c [addr]
1838 processor_t *p = sim->get_core(0);
1839 if (packet[2] != '#') {
1840 std::vector<uint8_t>::const_iterator iter = packet.begin() + 2;
1841 dpc = consume_hex_number(iter, packet.end());
1842 if (*iter != '#')
1843 return send_packet("E30");
1844 }
1845
1846 add_operation(new maybe_restore_tselect_op_t(*this));
1847 add_operation(new continue_op_t(*this, false));
1848 }
1849
1850 void gdbserver_t::handle_step(const std::vector<uint8_t> &packet)
1851 {
1852 // s [addr]
1853 if (packet[2] != '#') {
1854 std::vector<uint8_t>::const_iterator iter = packet.begin() + 2;
1855 die("handle_step");
1856 //p->state.pc = consume_hex_number(iter, packet.end());
1857 if (*iter != '#')
1858 return send_packet("E40");
1859 }
1860
1861 add_operation(new maybe_restore_tselect_op_t(*this));
1862 add_operation(new continue_op_t(*this, true));
1863 }
1864
1865 void gdbserver_t::handle_kill(const std::vector<uint8_t> &packet)
1866 {
1867 // k
1868 // The exact effect of this packet is not specified.
1869 // Looks like OpenOCD disconnects?
1870 // TODO
1871 }
1872
1873 void gdbserver_t::handle_extended(const std::vector<uint8_t> &packet)
1874 {
1875 // Enable extended mode. In extended mode, the remote server is made
1876 // persistent. The ‘R’ packet is used to restart the program being debugged.
1877 send_packet("OK");
1878 extended_mode = true;
1879 }
1880
1881 void gdbserver_t::software_breakpoint_insert(reg_t vaddr, unsigned int size)
1882 {
1883 fence_i_required = true;
1884 add_operation(new collect_translation_info_op_t(*this, vaddr, size));
1885 unsigned char* inst = new unsigned char[4];
1886 if (size == 2) {
1887 inst[0] = C_EBREAK & 0xff;
1888 inst[1] = (C_EBREAK >> 8) & 0xff;
1889 } else {
1890 inst[0] = EBREAK & 0xff;
1891 inst[1] = (EBREAK >> 8) & 0xff;
1892 inst[2] = (EBREAK >> 16) & 0xff;
1893 inst[3] = (EBREAK >> 24) & 0xff;
1894 }
1895
1896 software_breakpoint_t bp = {
1897 .vaddr = vaddr,
1898 .size = size
1899 };
1900 software_breakpoints[vaddr] = bp;
1901 add_operation(new memory_read_op_t(*this, bp.vaddr, bp.size,
1902 software_breakpoints[bp.vaddr].instruction));
1903 add_operation(new memory_write_op_t(*this, bp.vaddr, bp.size, inst));
1904 }
1905
1906 void gdbserver_t::software_breakpoint_remove(reg_t vaddr, unsigned int size)
1907 {
1908 fence_i_required = true;
1909 add_operation(new collect_translation_info_op_t(*this, vaddr, size));
1910
1911 software_breakpoint_t found_bp = software_breakpoints[vaddr];
1912 unsigned char* instruction = new unsigned char[4];
1913 memcpy(instruction, found_bp.instruction, 4);
1914 add_operation(new memory_write_op_t(*this, found_bp.vaddr,
1915 found_bp.size, instruction));
1916 software_breakpoints.erase(vaddr);
1917 }
1918
1919 void gdbserver_t::hardware_breakpoint_insert(const hardware_breakpoint_t &bp)
1920 {
1921 add_operation(new maybe_save_tselect_op_t(*this));
1922 add_operation(new hardware_breakpoint_insert_op_t(*this, bp));
1923 }
1924
1925 void gdbserver_t::hardware_breakpoint_remove(const hardware_breakpoint_t &bp)
1926 {
1927 add_operation(new maybe_save_tselect_op_t(*this));
1928 hardware_breakpoint_t found = *hardware_breakpoints.find(bp);
1929 add_operation(new hardware_breakpoint_remove_op_t(*this, found));
1930 }
1931
1932 void gdbserver_t::handle_breakpoint(const std::vector<uint8_t> &packet)
1933 {
1934 // insert: Z type,addr,length
1935 // remove: z type,addr,length
1936
1937 // type: 0 - software breakpoint, 1 - hardware breakpoint, 2 - write
1938 // watchpoint, 3 - read watchpoint, 4 - access watchpoint; addr is address;
1939 // length is in bytes. For a software breakpoint, length specifies the size
1940 // of the instruction to be patched. For hardware breakpoints and watchpoints
1941 // length specifies the memory region to be monitored. To avoid potential
1942 // problems with duplicate packets, the operations should be implemented in
1943 // an idempotent way.
1944
1945 bool insert = (packet[1] == 'Z');
1946 std::vector<uint8_t>::const_iterator iter = packet.begin() + 2;
1947 gdb_breakpoint_type_t type = static_cast<gdb_breakpoint_type_t>(
1948 consume_hex_number(iter, packet.end()));
1949 if (*iter != ',')
1950 return send_packet("E50");
1951 iter++;
1952 reg_t address = consume_hex_number(iter, packet.end());
1953 if (*iter != ',')
1954 return send_packet("E51");
1955 iter++;
1956 unsigned int size = consume_hex_number(iter, packet.end());
1957 // There may be more options after a ; here, but we don't support that.
1958 if (*iter != '#')
1959 return send_packet("E52");
1960
1961 switch (type) {
1962 case GB_SOFTWARE:
1963 if (size != 2 && size != 4) {
1964 return send_packet("E53");
1965 }
1966 if (insert) {
1967 software_breakpoint_insert(address, size);
1968 } else {
1969 software_breakpoint_remove(address, size);
1970 }
1971 break;
1972
1973 case GB_HARDWARE:
1974 case GB_WRITE:
1975 case GB_READ:
1976 case GB_ACCESS:
1977 {
1978 hardware_breakpoint_t bp = {
1979 .vaddr = address,
1980 .size = size
1981 };
1982 bp.load = (type == GB_READ || type == GB_ACCESS);
1983 bp.store = (type == GB_WRITE || type == GB_ACCESS);
1984 bp.execute = (type == GB_HARDWARE || type == GB_ACCESS);
1985 if (insert) {
1986 hardware_breakpoint_insert(bp);
1987 // Insert might fail if there's no space, so the insert operation will
1988 // send its own OK (or not).
1989 return;
1990 } else {
1991 hardware_breakpoint_remove(bp);
1992 }
1993 }
1994 break;
1995
1996 default:
1997 return send_packet("E56");
1998 }
1999
2000 return send_packet("OK");
2001 }
2002
2003 void gdbserver_t::handle_query(const std::vector<uint8_t> &packet)
2004 {
2005 std::string name;
2006 std::vector<uint8_t>::const_iterator iter = packet.begin() + 2;
2007
2008 consume_string(name, iter, packet.end(), ':');
2009 if (iter != packet.end())
2010 iter++;
2011 if (name == "Supported") {
2012 start_packet();
2013 while (iter != packet.end()) {
2014 std::string feature;
2015 consume_string(feature, iter, packet.end(), ';');
2016 if (iter != packet.end())
2017 iter++;
2018 if (feature == "swbreak+") {
2019 send("swbreak+;");
2020 }
2021 }
2022 send("PacketSize=131072;");
2023 return end_packet();
2024 }
2025
2026 D(fprintf(stderr, "Unsupported query %s\n", name.c_str()));
2027 return send_packet("");
2028 }
2029
2030 void gdbserver_t::handle_packet(const std::vector<uint8_t> &packet)
2031 {
2032 if (compute_checksum(packet) != extract_checksum(packet)) {
2033 fprintf(stderr, "Received %ld-byte packet with invalid checksum\n", packet.size());
2034 fprintf(stderr, "Computed checksum: %x\n", compute_checksum(packet));
2035 print_packet(packet);
2036 send("-");
2037 return;
2038 }
2039
2040 D(fprintf(stderr, "Received %ld-byte packet from debug client: ", packet.size()));
2041 D(print_packet(packet));
2042 send("+");
2043
2044 switch (packet[1]) {
2045 case '!':
2046 return handle_extended(packet);
2047 case '?':
2048 return handle_halt_reason(packet);
2049 case 'g':
2050 return handle_general_registers_read(packet);
2051 // case 'k':
2052 // return handle_kill(packet);
2053 case 'm':
2054 return handle_memory_read(packet);
2055 // case 'M':
2056 // return handle_memory_write(packet);
2057 case 'X':
2058 return handle_memory_binary_write(packet);
2059 case 'p':
2060 return handle_register_read(packet);
2061 case 'P':
2062 return handle_register_write(packet);
2063 case 'c':
2064 return handle_continue(packet);
2065 case 's':
2066 return handle_step(packet);
2067 case 'z':
2068 case 'Z':
2069 return handle_breakpoint(packet);
2070 case 'q':
2071 case 'Q':
2072 return handle_query(packet);
2073 }
2074
2075 // Not supported.
2076 D(fprintf(stderr, "** Unsupported packet: "));
2077 D(print_packet(packet));
2078 send_packet("");
2079 }
2080
2081 void gdbserver_t::handle_interrupt()
2082 {
2083 processor_t *p = sim->get_core(0);
2084 add_operation(new halt_op_t(*this, true));
2085 }
2086
2087 void gdbserver_t::handle()
2088 {
2089 if (client_fd > 0) {
2090 processor_t *p = sim->get_core(0);
2091
2092 bool interrupt = sim->debug_module.get_interrupt(0);
2093
2094 if (!interrupt && !operation_queue.empty()) {
2095 operation_t *operation = operation_queue.front();
2096 if (operation->step()) {
2097 operation_queue.pop();
2098 delete operation;
2099 }
2100 }
2101
2102 bool halt_notification = sim->debug_module.get_halt_notification(0);
2103 if (halt_notification) {
2104 sim->debug_module.clear_halt_notification(0);
2105 add_operation(new halt_op_t(*this, true));
2106 }
2107
2108 this->read();
2109 this->write();
2110
2111 } else {
2112 this->accept();
2113 }
2114
2115 if (operation_queue.empty()) {
2116 this->process_requests();
2117 }
2118 }
2119
2120 void gdbserver_t::send(const char* msg)
2121 {
2122 unsigned int length = strlen(msg);
2123 for (const char *c = msg; *c; c++)
2124 running_checksum += *c;
2125 send_buf.append((const uint8_t *) msg, length);
2126 }
2127
2128 void gdbserver_t::send(uint64_t value)
2129 {
2130 char buffer[3];
2131 for (unsigned int i = 0; i < 8; i++) {
2132 sprintf(buffer, "%02x", (int) (value & 0xff));
2133 send(buffer);
2134 value >>= 8;
2135 }
2136 }
2137
2138 void gdbserver_t::send(uint32_t value)
2139 {
2140 char buffer[3];
2141 for (unsigned int i = 0; i < 4; i++) {
2142 sprintf(buffer, "%02x", (int) (value & 0xff));
2143 send(buffer);
2144 value >>= 8;
2145 }
2146 }
2147
2148 void gdbserver_t::send(uint8_t value)
2149 {
2150 char buffer[3];
2151 sprintf(buffer, "%02x", (int) value);
2152 send(buffer);
2153 }
2154
2155 void gdbserver_t::send_packet(const char* data)
2156 {
2157 start_packet();
2158 send(data);
2159 end_packet();
2160 expect_ack = true;
2161 }
2162
2163 void gdbserver_t::start_packet()
2164 {
2165 send("$");
2166 running_checksum = 0;
2167 }
2168
2169 void gdbserver_t::end_packet(const char* data)
2170 {
2171 if (data) {
2172 send(data);
2173 }
2174
2175 char checksum_string[4];
2176 sprintf(checksum_string, "#%02x", running_checksum);
2177 send(checksum_string);
2178 expect_ack = true;
2179 }