riscv/gdbserver.cc

   1 #include <arpa/inet.h>
   2 #include <errno.h>
   3 #include <fcntl.h>
   4 #include <stdlib.h>
   5 #include <string.h>
   6 #include <sys/socket.h>
   7 #include <sys/types.h>
   8 #include <unistd.h>
   9
  10 #include <algorithm>
  11 #include <cassert>
  12 #include <cstdio>
  13 #include <vector>
  14
  15 #include "disasm.h"
  16 #include "sim.h"
  17 #include "gdbserver.h"
  18 #include "mmu.h"
  19
  20 #define C_EBREAK        0x9002
  21 #define EBREAK          0x00100073
  22
  23 //////////////////////////////////////// Utility Functions
  24
  25 #undef DEBUG
  26 #ifdef DEBUG
  27 #  define D(x) x
  28 #else
  29 #  define D(x)
  30 #endif // DEBUG
  31
  32 const int debug_gdbserver = 0;
  33
  34 void die(const char* msg)
  35 {
  36   fprintf(stderr, "gdbserver code died: %s\n", msg);
  37   abort();
  38 }
  39
  40 // gdb's register list is defined in riscv_gdb_reg_names gdb/riscv-tdep.c in
  41 // its source tree. We must interpret the numbers the same here.
  42 enum {
  43   REG_XPR0 = 0,
  44   REG_XPR31 = 31,
  45   REG_PC = 32,
  46   REG_FPR0 = 33,
  47   REG_FPR31 = 64,
  48   REG_CSR0 = 65,
  49   REG_CSR4095 = 4160,
  50   REG_END = 4161
  51 };
  52
  53 //////////////////////////////////////// Functions to generate RISC-V opcodes.
  54
  55 // TODO: Does this already exist somewhere?
  56
  57 #define ZERO    0
  58 // Using regnames.cc as source. The RVG Calling Convention of the 2.0 RISC-V
  59 // spec says it should be 2 and 3.
  60 #define S0      8
  61 #define S1      9
  62 static uint32_t bits(uint32_t value, unsigned int hi, unsigned int lo) {
  63   return (value >> lo) & ((1 << (hi+1-lo)) - 1);
  64 }
  65
  66 static uint32_t bit(uint32_t value, unsigned int b) {
  67   return (value >> b) & 1;
  68 }
  69
  70 static uint32_t jal(unsigned int rd, uint32_t imm) {
  71   return (bit(imm, 20) << 31) |
  72     (bits(imm, 10, 1) << 21) |
  73     (bit(imm, 11) << 20) |
  74     (bits(imm, 19, 12) << 12) |
  75     (rd << 7) |
  76     MATCH_JAL;
  77 }
  78
  79 static uint32_t csrsi(unsigned int csr, uint16_t imm) {
  80   return (csr << 20) |
  81     (bits(imm, 4, 0) << 15) |
  82     MATCH_CSRRSI;
  83 }
  84
  85 static uint32_t csrci(unsigned int csr, uint16_t imm) {
  86   return (csr << 20) |
  87     (bits(imm, 4, 0) << 15) |
  88     MATCH_CSRRCI;
  89 }
  90
  91 static uint32_t csrr(unsigned int rd, unsigned int csr) {
  92   return (csr << 20) | (rd << 7) | MATCH_CSRRS;
  93 }
  94
  95 static uint32_t csrw(unsigned int source, unsigned int csr) {
  96   return (csr << 20) | (source << 15) | MATCH_CSRRW;
  97 }
  98
  99 static uint32_t fence_i()
 100 {
 101   return MATCH_FENCE_I;
 102 }
 103
 104 static uint32_t sb(unsigned int src, unsigned int base, uint16_t offset)
 105 {
 106   return (bits(offset, 11, 5) << 25) |
 107     (src << 20) |
 108     (base << 15) |
 109     (bits(offset, 4, 0) << 7) |
 110     MATCH_SB;
 111 }
 112
 113 static uint32_t sh(unsigned int src, unsigned int base, uint16_t offset)
 114 {
 115   return (bits(offset, 11, 5) << 25) |
 116     (src << 20) |
 117     (base << 15) |
 118     (bits(offset, 4, 0) << 7) |
 119     MATCH_SH;
 120 }
 121
 122 static uint32_t sw(unsigned int src, unsigned int base, uint16_t offset)
 123 {
 124   return (bits(offset, 11, 5) << 25) |
 125     (src << 20) |
 126     (base << 15) |
 127     (bits(offset, 4, 0) << 7) |
 128     MATCH_SW;
 129 }
 130
 131 static uint32_t sd(unsigned int src, unsigned int base, uint16_t offset)
 132 {
 133   return (bits(offset, 11, 5) << 25) |
 134     (bits(src, 4, 0) << 20) |
 135     (base << 15) |
 136     (bits(offset, 4, 0) << 7) |
 137     MATCH_SD;
 138 }
 139
 140 static uint32_t sq(unsigned int src, unsigned int base, uint16_t offset)
 141 {
 142 #if 0
 143   return (bits(offset, 11, 5) << 25) |
 144     (bits(src, 4, 0) << 20) |
 145     (base << 15) |
 146     (bits(offset, 4, 0) << 7) |
 147     MATCH_SQ;
 148 #else
 149   abort();
 150 #endif
 151 }
 152
 153 static uint32_t lq(unsigned int rd, unsigned int base, uint16_t offset)
 154 {
 155 #if 0
 156   return (bits(offset, 11, 0) << 20) |
 157     (base << 15) |
 158     (bits(rd, 4, 0) << 7) |
 159     MATCH_LQ;
 160 #else
 161   abort();
 162 #endif
 163 }
 164
 165 static uint32_t ld(unsigned int rd, unsigned int base, uint16_t offset)
 166 {
 167   return (bits(offset, 11, 0) << 20) |
 168     (base << 15) |
 169     (bits(rd, 4, 0) << 7) |
 170     MATCH_LD;
 171 }
 172
 173 static uint32_t lw(unsigned int rd, unsigned int base, uint16_t offset)
 174 {
 175   return (bits(offset, 11, 0) << 20) |
 176     (base << 15) |
 177     (bits(rd, 4, 0) << 7) |
 178     MATCH_LW;
 179 }
 180
 181 static uint32_t lh(unsigned int rd, unsigned int base, uint16_t offset)
 182 {
 183   return (bits(offset, 11, 0) << 20) |
 184     (base << 15) |
 185     (bits(rd, 4, 0) << 7) |
 186     MATCH_LH;
 187 }
 188
 189 static uint32_t lb(unsigned int rd, unsigned int base, uint16_t offset)
 190 {
 191   return (bits(offset, 11, 0) << 20) |
 192     (base << 15) |
 193     (bits(rd, 4, 0) << 7) |
 194     MATCH_LB;
 195 }
 196
 197 static uint32_t fsw(unsigned int src, unsigned int base, uint16_t offset)
 198 {
 199   return (bits(offset, 11, 5) << 25) |
 200     (bits(src, 4, 0) << 20) |
 201     (base << 15) |
 202     (bits(offset, 4, 0) << 7) |
 203     MATCH_FSW;
 204 }
 205
 206 static uint32_t fsd(unsigned int src, unsigned int base, uint16_t offset)
 207 {
 208   return (bits(offset, 11, 5) << 25) |
 209     (bits(src, 4, 0) << 20) |
 210     (base << 15) |
 211     (bits(offset, 4, 0) << 7) |
 212     MATCH_FSD;
 213 }
 214
 215 static uint32_t flw(unsigned int src, unsigned int base, uint16_t offset)
 216 {
 217   return (bits(offset, 11, 5) << 25) |
 218     (bits(src, 4, 0) << 20) |
 219     (base << 15) |
 220     (bits(offset, 4, 0) << 7) |
 221     MATCH_FLW;
 222 }
 223
 224 static uint32_t fld(unsigned int src, unsigned int base, uint16_t offset)
 225 {
 226   return (bits(offset, 11, 5) << 25) |
 227     (bits(src, 4, 0) << 20) |
 228     (base << 15) |
 229     (bits(offset, 4, 0) << 7) |
 230     MATCH_FLD;
 231 }
 232
 233 static uint32_t addi(unsigned int dest, unsigned int src, uint16_t imm)
 234 {
 235   return (bits(imm, 11, 0) << 20) |
 236     (src << 15) |
 237     (dest << 7) |
 238     MATCH_ADDI;
 239 }
 240
 241 static uint32_t ori(unsigned int dest, unsigned int src, uint16_t imm)
 242 {
 243   return (bits(imm, 11, 0) << 20) |
 244     (src << 15) |
 245     (dest << 7) |
 246     MATCH_ORI;
 247 }
 248
 249 static uint32_t xori(unsigned int dest, unsigned int src, uint16_t imm)
 250 {
 251   return (bits(imm, 11, 0) << 20) |
 252     (src << 15) |
 253     (dest << 7) |
 254     MATCH_XORI;
 255 }
 256
 257 static uint32_t srli(unsigned int dest, unsigned int src, uint8_t shamt)
 258 {
 259   return (bits(shamt, 4, 0) << 20) |
 260     (src << 15) |
 261     (dest << 7) |
 262     MATCH_SRLI;
 263 }
 264
 265
 266 static uint32_t nop()
 267 {
 268   return addi(0, 0, 0);
 269 }
 270
 271 template <typename T>
 272 unsigned int circular_buffer_t<T>::size() const
 273 {
 274   if (end >= start)
 275     return end - start;
 276   else
 277     return end + capacity - start;
 278 }
 279
 280 template <typename T>
 281 void circular_buffer_t<T>::consume(unsigned int bytes)
 282 {
 283   start = (start + bytes) % capacity;
 284 }
 285
 286 template <typename T>
 287 unsigned int circular_buffer_t<T>::contiguous_empty_size() const
 288 {
 289   if (end >= start)
 290     if (start == 0)
 291       return capacity - end - 1;
 292     else
 293       return capacity - end;
 294   else
 295     return start - end - 1;
 296 }
 297
 298 template <typename T>
 299 unsigned int circular_buffer_t<T>::contiguous_data_size() const
 300 {
 301   if (end >= start)
 302     return end - start;
 303   else
 304     return capacity - start;
 305 }
 306
 307 template <typename T>
 308 void circular_buffer_t<T>::data_added(unsigned int bytes)
 309 {
 310   end += bytes;
 311   assert(end <= capacity);
 312   if (end == capacity)
 313     end = 0;
 314 }
 315
 316 template <typename T>
 317 void circular_buffer_t<T>::reset()
 318 {
 319   start = 0;
 320   end = 0;
 321 }
 322
 323 template <typename T>
 324 void circular_buffer_t<T>::append(const T *src, unsigned int count)
 325 {
 326   unsigned int copy = std::min(count, contiguous_empty_size());
 327   memcpy(contiguous_empty(), src, copy * sizeof(T));
 328   data_added(copy);
 329   count -= copy;
 330   if (count > 0) {
 331     assert(count < contiguous_empty_size());
 332     memcpy(contiguous_empty(), src, count * sizeof(T));
 333     data_added(count);
 334   }
 335 }
 336
 337 ////////////////////////////// Debug Operations
 338
 339 class halt_op_t : public operation_t
 340 {
 341   public:
 342     halt_op_t(gdbserver_t& gdbserver, bool send_status=false) :
 343       operation_t(gdbserver), send_status(send_status),
 344       state(ST_ENTER) {};
 345
 346     void write_dpc_program() {
 347       gs.dr_write32(0, csrsi(CSR_DCSR, DCSR_HALT));
 348       gs.dr_write32(1, csrr(S0, CSR_DPC));
 349       gs.dr_write_store(2, S0, SLOT_DATA0);
 350       gs.dr_write_jump(3);
 351       gs.set_interrupt(0);
 352     }
 353
 354     bool perform_step(unsigned int step) {
 355       switch (state) {
 356         case ST_ENTER:
 357           if (gs.xlen == 0) {
 358             gs.dr_write32(0, xori(S1, ZERO, -1));
 359             gs.dr_write32(1, srli(S1, S1, 31));
 360             // 0x00000001  0x00000001:ffffffff  0x00000001:ffffffff:ffffffff:ffffffff
 361             gs.dr_write32(2, sw(S1, ZERO, DEBUG_RAM_START));
 362             gs.dr_write32(3, srli(S1, S1, 31));
 363             // 0x00000000  0x00000000:00000003  0x00000000:00000003:ffffffff:ffffffff
 364             gs.dr_write32(4, sw(S1, ZERO, DEBUG_RAM_START + 4));
 365             gs.dr_write_jump(5);
 366             gs.set_interrupt(0);
 367             state = ST_XLEN;
 368
 369           } else {
 370             write_dpc_program();
 371             state = ST_DPC;
 372           }
 373           return false;
 374
 375         case ST_XLEN:
 376           {
 377             uint32_t word0 = gs.dr_read32(0);
 378             uint32_t word1 = gs.dr_read32(1);
 379
 380             if (word0 == 1 && word1 == 0) {
 381               gs.xlen = 32;
 382             } else if (word0 == 0xffffffff && word1 == 3) {
 383               gs.xlen = 64;
 384             } else if (word0 == 0xffffffff && word1 == 0xffffffff) {
 385               gs.xlen = 128;
 386             }
 387
 388             write_dpc_program();
 389             state = ST_DPC;
 390             return false;
 391           }
 392
 393         case ST_DPC:
 394           gs.dpc = gs.dr_read(SLOT_DATA0);
 395           fprintf(stderr, "dpc=0x%lx\n", gs.dpc);
 396           gs.dr_write32(0, csrr(S0, CSR_MSTATUS));
 397           gs.dr_write_store(1, S0, SLOT_DATA0);
 398           gs.dr_write_jump(2);
 399           gs.set_interrupt(0);
 400           state = ST_MSTATUS;
 401           return false;
 402
 403         case ST_MSTATUS:
 404           gs.mstatus = gs.dr_read(SLOT_DATA0);
 405           gs.dr_write32(0, csrr(S0, CSR_DCSR));
 406           gs.dr_write32(1, sw(S0, 0, (uint16_t) DEBUG_RAM_START + 16));
 407           gs.dr_write_jump(2);
 408           gs.set_interrupt(0);
 409           state = ST_DCSR;
 410           return false;
 411
 412         case ST_DCSR:
 413           gs.dcsr = gs.dr_read32(4);
 414
 415           gs.sptbr_valid = false;
 416           gs.pte_cache.clear();
 417
 418           if (send_status) {
 419             switch (get_field(gs.dcsr, DCSR_CAUSE)) {
 420               case DCSR_CAUSE_NONE:
 421                 fprintf(stderr, "Internal error. Processor halted without reason.\n");
 422                 abort();
 423
 424               case DCSR_CAUSE_DEBUGINT:
 425                 gs.send_packet("S02");   // Pretend program received SIGINT.
 426                 break;
 427
 428               case DCSR_CAUSE_HWBP:
 429               case DCSR_CAUSE_STEP:
 430               case DCSR_CAUSE_HALT:
 431                 // There's no gdb code for this.
 432                 gs.send_packet("T05");
 433                 break;
 434               case DCSR_CAUSE_SWBP:
 435                 gs.send_packet("T05swbreak:;");
 436                 break;
 437             }
 438           }
 439           return true;
 440
 441         default:
 442           assert(0);
 443       }
 444     }
 445
 446   private:
 447     bool send_status;
 448     enum {
 449       ST_ENTER,
 450       ST_XLEN,
 451       ST_DPC,
 452       ST_MSTATUS,
 453       ST_DCSR
 454     } state;
 455 };
 456
 457 class continue_op_t : public operation_t
 458 {
 459   public:
 460     continue_op_t(gdbserver_t& gdbserver, bool single_step) :
 461       operation_t(gdbserver), single_step(single_step) {};
 462
 463     bool perform_step(unsigned int step) {
 464       switch (step) {
 465         case 0:
 466           gs.dr_write_load(0, S0, SLOT_DATA0);
 467           gs.dr_write32(1, csrw(S0, CSR_DPC));
 468           // TODO: Isn't there a fence.i in Debug ROM already?
 469           if (gs.fence_i_required) {
 470             gs.dr_write32(2, fence_i());
 471             gs.dr_write_jump(3);
 472             gs.fence_i_required = false;
 473           } else {
 474             gs.dr_write_jump(2);
 475           }
 476           gs.dr_write(SLOT_DATA0, gs.dpc);
 477           gs.set_interrupt(0);
 478           return false;
 479
 480         case 1:
 481           gs.dr_write_load(0, S0, SLOT_DATA0);
 482           gs.dr_write32(1, csrw(S0, CSR_MSTATUS));
 483           gs.dr_write_jump(2);
 484           gs.dr_write(SLOT_DATA0, gs.mstatus);
 485           gs.set_interrupt(0);
 486           return false;
 487
 488         case 2:
 489           gs.dr_write32(0, lw(S0, 0, (uint16_t) DEBUG_RAM_START+16));
 490           gs.dr_write32(1, csrw(S0, CSR_DCSR));
 491           gs.dr_write_jump(2);
 492
 493           reg_t dcsr = set_field(gs.dcsr, DCSR_HALT, 0);
 494           dcsr = set_field(dcsr, DCSR_STEP, single_step);
 495           // Software breakpoints should go here.
 496           dcsr = set_field(dcsr, DCSR_EBREAKM, 1);
 497           dcsr = set_field(dcsr, DCSR_EBREAKH, 1);
 498           dcsr = set_field(dcsr, DCSR_EBREAKS, 1);
 499           dcsr = set_field(dcsr, DCSR_EBREAKU, 1);
 500           gs.dr_write32(4, dcsr);
 501
 502           gs.set_interrupt(0);
 503           return true;
 504       }
 505       return false;
 506     }
 507
 508   private:
 509     bool single_step;
 510 };
 511
 512 class general_registers_read_op_t : public operation_t
 513 {
 514   // Register order that gdb expects is:
 515   //   "x0",  "x1",  "x2",  "x3",  "x4",  "x5",  "x6",  "x7",
 516   //   "x8",  "x9",  "x10", "x11", "x12", "x13", "x14", "x15",
 517   //   "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
 518   //   "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31",
 519
 520   // Each byte of register data is described by two hex digits. The bytes with
 521   // the register are transmitted in target byte order. The size of each
 522   // register and their position within the ‘g’ packet are determined by the
 523   // gdb internal gdbarch functions DEPRECATED_REGISTER_RAW_SIZE and
 524   // gdbarch_register_name.
 525
 526   public:
 527     general_registers_read_op_t(gdbserver_t& gdbserver) :
 528       operation_t(gdbserver) {};
 529
 530     bool perform_step(unsigned int step)
 531     {
 532       if (step == 0) {
 533         gs.start_packet();
 534
 535         // x0 is always zero.
 536         if (gs.xlen == 32) {
 537           gs.send((uint32_t) 0);
 538         } else {
 539           gs.send((uint64_t) 0);
 540         }
 541
 542         gs.dr_write_store(0, 1, SLOT_DATA0);
 543         gs.dr_write_store(1, 2, SLOT_DATA1);
 544         gs.dr_write_jump(2);
 545         gs.set_interrupt(0);
 546         return false;
 547       }
 548
 549       if (gs.xlen == 32) {
 550         gs.send((uint32_t) gs.dr_read(SLOT_DATA0));
 551       } else {
 552         gs.send((uint64_t) gs.dr_read(SLOT_DATA0));
 553       }
 554       if (step >= 16) {
 555         gs.end_packet();
 556         return true;
 557       }
 558
 559       if (gs.xlen == 32) {
 560         gs.send((uint32_t) gs.dr_read(SLOT_DATA1));
 561       } else {
 562         gs.send((uint64_t) gs.dr_read(SLOT_DATA1));
 563       }
 564
 565       unsigned int current_reg = 2 * step + 1;
 566       unsigned int i = 0;
 567       if (current_reg == S1) {
 568         gs.dr_write_load(i++, S1, SLOT_DATA_LAST);
 569       }
 570       gs.dr_write_store(i++, current_reg, SLOT_DATA0);
 571       if (current_reg + 1 == S0) {
 572         gs.dr_write32(i++, csrr(S0, CSR_DSCRATCH));
 573       }
 574       gs.dr_write_store(i++, current_reg+1, SLOT_DATA1);
 575       gs.dr_write_jump(i);
 576       gs.set_interrupt(0);
 577
 578       return false;
 579     }
 580 };
 581
 582 class register_read_op_t : public operation_t
 583 {
 584   public:
 585     register_read_op_t(gdbserver_t& gdbserver, unsigned int reg) :
 586       operation_t(gdbserver), reg(reg) {};
 587
 588     bool perform_step(unsigned int step)
 589     {
 590       switch (step) {
 591         case 0:
 592           if (reg >= REG_XPR0 && reg <= REG_XPR31) {
 593             die("handle_register_read");
 594             // send(p->state.XPR[reg - REG_XPR0]);
 595           } else if (reg == REG_PC) {
 596             gs.start_packet();
 597             if (gs.xlen == 32) {
 598               gs.send((uint32_t) gs.dpc);
 599             } else {
 600               gs.send(gs.dpc);
 601             }
 602             gs.end_packet();
 603             return true;
 604           } else if (reg >= REG_FPR0 && reg <= REG_FPR31) {
 605             // send(p->state.FPR[reg - REG_FPR0]);
 606             if (gs.xlen == 32) {
 607               gs.dr_write32(0, fsw(reg - REG_FPR0, 0, (uint16_t) DEBUG_RAM_START + 16));
 608             } else {
 609               gs.dr_write32(0, fsd(reg - REG_FPR0, 0, (uint16_t) DEBUG_RAM_START + 16));
 610             }
 611             gs.dr_write_jump(1);
 612           } else if (reg >= REG_CSR0 && reg <= REG_CSR4095) {
 613             gs.dr_write32(0, csrr(S0, reg - REG_CSR0));
 614             gs.dr_write_store(1, S0, SLOT_DATA0);
 615             gs.dr_write_jump(2);
 616             // If we hit an exception reading the CSR, we'll end up returning ~0 as
 617             // the register's value, which is what we want. (Right?)
 618             gs.dr_write(SLOT_DATA0, ~(uint64_t) 0);
 619           } else {
 620             gs.send_packet("E02");
 621             return true;
 622           }
 623           gs.set_interrupt(0);
 624           return false;
 625
 626         case 1:
 627           gs.start_packet();
 628           if (gs.xlen == 32) {
 629             gs.send(gs.dr_read32(4));
 630           } else {
 631             gs.send(gs.dr_read(SLOT_DATA0));
 632           }
 633           gs.end_packet();
 634           return true;
 635       }
 636       return false;
 637     }
 638
 639   private:
 640     unsigned int reg;
 641 };
 642
 643 class register_write_op_t : public operation_t
 644 {
 645   public:
 646     register_write_op_t(gdbserver_t& gdbserver, unsigned int reg, reg_t value) :
 647       operation_t(gdbserver), reg(reg), value(value) {};
 648
 649     bool perform_step(unsigned int step)
 650     {
 651       gs.dr_write_load(0, S0, SLOT_DATA0);
 652       gs.dr_write(SLOT_DATA0, value);
 653       if (reg == S0) {
 654         gs.dr_write32(1, csrw(S0, CSR_DSCRATCH));
 655         gs.dr_write_jump(2);
 656       } else if (reg == S1) {
 657         gs.dr_write_store(1, S0, SLOT_DATA_LAST);
 658         gs.dr_write_jump(2);
 659       } else if (reg >= REG_XPR0 && reg <= REG_XPR31) {
 660         gs.dr_write32(1, addi(reg, S0, 0));
 661         gs.dr_write_jump(2);
 662       } else if (reg == REG_PC) {
 663         gs.dpc = value;
 664         return true;
 665       } else if (reg >= REG_FPR0 && reg <= REG_FPR31) {
 666         if (gs.xlen == 32) {
 667           gs.dr_write32(0, flw(reg - REG_FPR0, 0, (uint16_t) DEBUG_RAM_START + 16));
 668         } else {
 669           gs.dr_write32(0, fld(reg - REG_FPR0, 0, (uint16_t) DEBUG_RAM_START + 16));
 670         }
 671         gs.dr_write_jump(1);
 672       } else if (reg >= REG_CSR0 && reg <= REG_CSR4095) {
 673         gs.dr_write32(1, csrw(S0, reg - REG_CSR0));
 674         gs.dr_write_jump(2);
 675         if (reg == REG_CSR0 + CSR_SPTBR) {
 676           gs.sptbr = value;
 677           gs.sptbr_valid = true;
 678         }
 679       } else {
 680         gs.send_packet("E02");
 681         return true;
 682       }
 683       gs.set_interrupt(0);
 684       gs.send_packet("OK");
 685       return true;
 686     }
 687
 688   private:
 689     unsigned int reg;
 690     reg_t value;
 691 };
 692
 693 class memory_read_op_t : public operation_t
 694 {
 695   public:
 696     // Read length bytes from vaddr, storing the result into data.
 697     // If data is NULL, send the result straight to gdb.
 698     memory_read_op_t(gdbserver_t& gdbserver, reg_t vaddr, unsigned int length,
 699         unsigned char *data=NULL) :
 700       operation_t(gdbserver), vaddr(vaddr), length(length), data(data) {};
 701
 702     bool perform_step(unsigned int step)
 703     {
 704       if (step == 0) {
 705         // address goes in S0
 706         paddr = gs.translate(vaddr);
 707         access_size = gs.find_access_size(paddr, length);
 708
 709         gs.dr_write_load(0, S0, SLOT_DATA0);
 710         switch (access_size) {
 711           case 1:
 712             gs.dr_write32(1, lb(S1, S0, 0));
 713             break;
 714           case 2:
 715             gs.dr_write32(1, lh(S1, S0, 0));
 716             break;
 717           case 4:
 718             gs.dr_write32(1, lw(S1, S0, 0));
 719             break;
 720           case 8:
 721             gs.dr_write32(1, ld(S1, S0, 0));
 722             break;
 723         }
 724         gs.dr_write_store(2, S1, SLOT_DATA1);
 725         gs.dr_write_jump(3);
 726         gs.dr_write(SLOT_DATA0, paddr);
 727         gs.set_interrupt(0);
 728
 729         if (!data) {
 730           gs.start_packet();
 731         }
 732         return false;
 733       }
 734
 735       char buffer[3];
 736       reg_t value = gs.dr_read(SLOT_DATA1);
 737       for (unsigned int i = 0; i < access_size; i++) {
 738         if (data) {
 739           *(data++) = value & 0xff;
 740           D(fprintf(stderr, "%02x", (unsigned int) (value & 0xff)));
 741         } else {
 742           sprintf(buffer, "%02x", (unsigned int) (value & 0xff));
 743           gs.send(buffer);
 744         }
 745         value >>= 8;
 746       }
 747       if (data && debug_gdbserver) {
 748         D(fprintf(stderr, "\n"));
 749       }
 750       length -= access_size;
 751       paddr += access_size;
 752
 753       if (length == 0) {
 754         if (!data) {
 755           gs.end_packet();
 756         }
 757         return true;
 758       } else {
 759         gs.dr_write(SLOT_DATA0, paddr);
 760         gs.set_interrupt(0);
 761         return false;
 762       }
 763     }
 764
 765   private:
 766     reg_t vaddr;
 767     unsigned int length;
 768     unsigned char* data;
 769     reg_t paddr;
 770     unsigned int access_size;
 771 };
 772
 773 class memory_write_op_t : public operation_t
 774 {
 775   public:
 776     memory_write_op_t(gdbserver_t& gdbserver, reg_t vaddr, unsigned int length,
 777         const unsigned char *data) :
 778       operation_t(gdbserver), vaddr(vaddr), offset(0), length(length), data(data) {};
 779
 780     ~memory_write_op_t() {
 781       delete[] data;
 782     }
 783
 784     bool perform_step(unsigned int step)
 785     {
 786       reg_t paddr = gs.translate(vaddr);
 787       if (step == 0) {
 788         access_size = gs.find_access_size(paddr, length);
 789
 790         D(fprintf(stderr, "write to 0x%lx -> 0x%lx (access=%d): ", vaddr, paddr,
 791             access_size));
 792         for (unsigned int i = 0; i < length; i++) {
 793           D(fprintf(stderr, "%02x", data[i]));
 794         }
 795         D(fprintf(stderr, "\n"));
 796
 797         // address goes in S0
 798         gs.dr_write_load(0, S0, SLOT_DATA0);
 799         switch (access_size) {
 800           case 1:
 801             gs.dr_write32(1, lb(S1, 0, (uint16_t) DEBUG_RAM_START + 24));
 802             gs.dr_write32(2, sb(S1, S0, 0));
 803             gs.dr_write32(6, data[0]);
 804             break;
 805           case 2:
 806             gs.dr_write32(1, lh(S1, 0, (uint16_t) DEBUG_RAM_START + 24));
 807             gs.dr_write32(2, sh(S1, S0, 0));
 808             gs.dr_write32(6, data[0] | (data[1] << 8));
 809             break;
 810           case 4:
 811             gs.dr_write32(1, lw(S1, 0, (uint16_t) DEBUG_RAM_START + 24));
 812             gs.dr_write32(2, sw(S1, S0, 0));
 813             gs.dr_write32(6, data[0] | (data[1] << 8) |
 814                 (data[2] << 16) | (data[3] << 24));
 815             break;
 816           case 8:
 817             gs.dr_write32(1, ld(S1, 0, (uint16_t) DEBUG_RAM_START + 24));
 818             gs.dr_write32(2, sd(S1, S0, 0));
 819             gs.dr_write32(6, data[0] | (data[1] << 8) |
 820                 (data[2] << 16) | (data[3] << 24));
 821             gs.dr_write32(7, data[4] | (data[5] << 8) |
 822                 (data[6] << 16) | (data[7] << 24));
 823             break;
 824           default:
 825             fprintf(stderr, "gdbserver error: write %d bytes to 0x%lx -> 0x%lx; "
 826                 "access_size=%d\n", length, vaddr, paddr, access_size);
 827             gs.send_packet("E12");
 828             return true;
 829         }
 830         gs.dr_write_jump(3);
 831         gs.dr_write(SLOT_DATA0, paddr);
 832         gs.set_interrupt(0);
 833
 834         return false;
 835       }
 836
 837       if (gs.dr_read32(DEBUG_RAM_SIZE / 4 - 1)) {
 838         fprintf(stderr, "Exception happened while writing to 0x%lx -> 0x%lx\n",
 839             vaddr, paddr);
 840       }
 841
 842       offset += access_size;
 843       if (offset >= length) {
 844         gs.send_packet("OK");
 845         return true;
 846       } else {
 847         const unsigned char *d = data + offset;
 848         switch (access_size) {
 849           case 1:
 850             gs.dr_write32(6, d[0]);
 851             break;
 852           case 2:
 853             gs.dr_write32(6, d[0] | (d[1] << 8));
 854             break;
 855           case 4:
 856             gs.dr_write32(6, d[0] | (d[1] << 8) |
 857                 (d[2] << 16) | (d[3] << 24));
 858             break;
 859           case 8:
 860             gs.dr_write32(6, d[0] | (d[1] << 8) |
 861                 (d[2] << 16) | (d[3] << 24));
 862             gs.dr_write32(7, d[4] | (d[5] << 8) |
 863                 (d[6] << 16) | (d[7] << 24));
 864             break;
 865           default:
 866             gs.send_packet("E13");
 867             return true;
 868         }
 869         gs.dr_write(SLOT_DATA0, paddr + offset);
 870         gs.set_interrupt(0);
 871         return false;
 872       }
 873     }
 874
 875   private:
 876     reg_t vaddr;
 877     unsigned int offset;
 878     unsigned int length;
 879     unsigned int access_size;
 880     const unsigned char *data;
 881 };
 882
 883 class collect_translation_info_op_t : public operation_t
 884 {
 885   public:
 886     // Read sufficient information from the target into gdbserver structures so
 887     // that it's possible to translate vaddr, vaddr+length, and all addresses
 888     // in between to physical addresses.
 889     collect_translation_info_op_t(gdbserver_t& gdbserver, reg_t vaddr, size_t length) :
 890       operation_t(gdbserver), state(STATE_START), vaddr(vaddr), length(length) {};
 891
 892     bool perform_step(unsigned int step)
 893     {
 894       unsigned int vm = gs.virtual_memory();
 895
 896       if (step == 0) {
 897         switch (vm) {
 898           case VM_MBARE:
 899             // Nothing to be done.
 900             return true;
 901
 902           case VM_SV32:
 903             levels = 2;
 904             ptidxbits = 10;
 905             ptesize = 4;
 906             break;
 907           case VM_SV39:
 908             levels = 3;
 909             ptidxbits = 9;
 910             ptesize = 8;
 911             break;
 912           case VM_SV48:
 913             levels = 4;
 914             ptidxbits = 9;
 915             ptesize = 8;
 916             break;
 917
 918           default:
 919             {
 920               char buf[100];
 921               sprintf(buf, "VM mode %d is not supported by gdbserver.cc.", vm);
 922               die(buf);
 923               return true;        // die doesn't return, but gcc doesn't know that.
 924             }
 925         }
 926       }
 927
 928       // Perform any reads from the just-completed action.
 929       switch (state) {
 930         case STATE_START:
 931           break;
 932         case STATE_READ_SPTBR:
 933           gs.sptbr = ((uint64_t) gs.dr_read32(5) << 32) | gs.dr_read32(4);
 934           gs.sptbr_valid = true;
 935           break;
 936         case STATE_READ_PTE:
 937           gs.pte_cache[pte_addr] = ((uint64_t) gs.dr_read32(5) << 32) |
 938             gs.dr_read32(4);
 939           D(fprintf(stderr, "pte_cache[0x%lx] = 0x%lx\n", pte_addr, gs.pte_cache[pte_addr]));
 940           break;
 941       }
 942
 943       // Set up the next action.
 944       // We only get here for VM_SV32/39/38.
 945
 946       if (!gs.sptbr_valid) {
 947         state = STATE_READ_SPTBR;
 948         gs.dr_write32(0, csrr(S0, CSR_SPTBR));
 949         gs.dr_write32(1, sd(S0, 0, (uint16_t) DEBUG_RAM_START + 16));
 950         gs.dr_write32(2, jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*2))));
 951         gs.set_interrupt(0);
 952         return false;
 953       }
 954
 955       reg_t base = gs.sptbr << PGSHIFT;
 956       int ptshift = (levels - 1) * ptidxbits;
 957       for (unsigned int i = 0; i < levels; i++, ptshift -= ptidxbits) {
 958         reg_t idx = (vaddr >> (PGSHIFT + ptshift)) & ((1 << ptidxbits) - 1);
 959
 960         pte_addr = base + idx * ptesize;
 961         auto it = gs.pte_cache.find(pte_addr);
 962         if (it == gs.pte_cache.end()) {
 963           state = STATE_READ_PTE;
 964           if (ptesize == 4) {
 965             gs.dr_write32(0, lw(S0, 0, (uint16_t) DEBUG_RAM_START + 16));
 966             gs.dr_write32(1, lw(S1, S0, 0));
 967             gs.dr_write32(2, sw(S1, 0, (uint16_t) DEBUG_RAM_START + 16));
 968           } else {
 969             assert(gs.xlen >= 64);
 970             gs.dr_write32(0, ld(S0, 0, (uint16_t) DEBUG_RAM_START + 16));
 971             gs.dr_write32(1, ld(S1, S0, 0));
 972             gs.dr_write32(2, sd(S1, 0, (uint16_t) DEBUG_RAM_START + 16));
 973           }
 974           gs.dr_write32(3, jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*3))));
 975           gs.dr_write32(4, pte_addr);
 976           gs.dr_write32(5, pte_addr >> 32);
 977           gs.set_interrupt(0);
 978           return false;
 979         }
 980
 981         reg_t pte = gs.pte_cache[pte_addr];
 982         reg_t ppn = pte >> PTE_PPN_SHIFT;
 983
 984         if (PTE_TABLE(pte)) { // next level of page table
 985           base = ppn << PGSHIFT;
 986         } else {
 987           // We've collected all the data required for the translation.
 988           return true;
 989         }
 990       }
 991       fprintf(stderr,
 992           "ERROR: gdbserver couldn't find appropriate PTEs to translate 0x%lx\n",
 993           vaddr);
 994       return true;
 995     }
 996
 997   private:
 998     enum {
 999       STATE_START,
1000       STATE_READ_SPTBR,
1001       STATE_READ_PTE
1002     } state;
1003     reg_t vaddr;
1004     size_t length;
1005     unsigned int levels;
1006     unsigned int ptidxbits;
1007     unsigned int ptesize;
1008     reg_t pte_addr;
1009 };
1010
1011 ////////////////////////////// gdbserver itself
1012
1013 gdbserver_t::gdbserver_t(uint16_t port, sim_t *sim) :
1014   xlen(0),
1015   sim(sim),
1016   client_fd(0),
1017   recv_buf(64 * 1024), send_buf(64 * 1024)
1018 {
1019   socket_fd = socket(AF_INET, SOCK_STREAM, 0);
1020   if (socket_fd == -1) {
1021     fprintf(stderr, "failed to make socket: %s (%d)\n", strerror(errno), errno);
1022     abort();
1023   }
1024
1025   fcntl(socket_fd, F_SETFL, O_NONBLOCK);
1026   int reuseaddr = 1;
1027   if (setsockopt(socket_fd, SOL_SOCKET, SO_REUSEADDR, &reuseaddr,
1028         sizeof(int)) == -1) {
1029     fprintf(stderr, "failed setsockopt: %s (%d)\n", strerror(errno), errno);
1030     abort();
1031   }
1032
1033   struct sockaddr_in addr;
1034   memset(&addr, 0, sizeof(addr));
1035   addr.sin_family = AF_INET;
1036   addr.sin_addr.s_addr = INADDR_ANY;
1037   addr.sin_port = htons(port);
1038
1039   if (bind(socket_fd, (struct sockaddr *) &addr, sizeof(addr)) == -1) {
1040     fprintf(stderr, "failed to bind socket: %s (%d)\n", strerror(errno), errno);
1041     abort();
1042   }
1043
1044   if (listen(socket_fd, 1) == -1) {
1045     fprintf(stderr, "failed to listen on socket: %s (%d)\n", strerror(errno), errno);
1046     abort();
1047   }
1048 }
1049
1050 unsigned int gdbserver_t::find_access_size(reg_t address, int length)
1051 {
1052   reg_t composite = address | length;
1053   if ((composite & 0x7) == 0 && xlen >= 64)
1054     return 8;
1055   if ((composite & 0x3) == 0)
1056     return 4;
1057   return 1;
1058 }
1059
1060 reg_t gdbserver_t::translate(reg_t vaddr)
1061 {
1062   unsigned int vm = virtual_memory();
1063   unsigned int levels, ptidxbits, ptesize;
1064
1065   switch (vm) {
1066     case VM_MBARE:
1067       return vaddr;
1068
1069     case VM_SV32:
1070       levels = 2;
1071       ptidxbits = 10;
1072       ptesize = 4;
1073       break;
1074     case VM_SV39:
1075       levels = 3;
1076       ptidxbits = 9;
1077       ptesize = 8;
1078       break;
1079     case VM_SV48:
1080       levels = 4;
1081       ptidxbits = 9;
1082       ptesize = 8;
1083       break;
1084
1085     default:
1086       {
1087         char buf[100];
1088         sprintf(buf, "VM mode %d is not supported by gdbserver.cc.", vm);
1089         die(buf);
1090         return true;        // die doesn't return, but gcc doesn't know that.
1091       }
1092   }
1093
1094   // Handle page tables here. There's a bunch of duplicated code with
1095   // collect_translation_info_op_t. :-(
1096   reg_t base = sptbr << PGSHIFT;
1097   int ptshift = (levels - 1) * ptidxbits;
1098   for (unsigned int i = 0; i < levels; i++, ptshift -= ptidxbits) {
1099     reg_t idx = (vaddr >> (PGSHIFT + ptshift)) & ((1 << ptidxbits) - 1);
1100
1101     reg_t pte_addr = base + idx * ptesize;
1102     auto it = pte_cache.find(pte_addr);
1103     if (it == pte_cache.end()) {
1104       fprintf(stderr, "ERROR: gdbserver tried to translate 0x%lx without first "
1105           "collecting the relevant PTEs.\n", vaddr);
1106       die("gdbserver_t::translate()");
1107     }
1108
1109     reg_t pte = pte_cache[pte_addr];
1110     reg_t ppn = pte >> PTE_PPN_SHIFT;
1111
1112     if (PTE_TABLE(pte)) { // next level of page table
1113       base = ppn << PGSHIFT;
1114     } else {
1115       // We've collected all the data required for the translation.
1116       reg_t vpn = vaddr >> PGSHIFT;
1117       reg_t paddr = (ppn | (vpn & ((reg_t(1) << ptshift) - 1))) << PGSHIFT;
1118       paddr += vaddr & (PGSIZE-1);
1119       D(fprintf(stderr, "gdbserver translate 0x%lx -> 0x%lx\n", vaddr, paddr));
1120       return paddr;
1121     }
1122   }
1123
1124   fprintf(stderr, "ERROR: gdbserver tried to translate 0x%lx but the relevant "
1125       "PTEs are invalid.\n", vaddr);
1126   // TODO: Is it better to throw an exception here?
1127   return -1;
1128 }
1129
1130 unsigned int gdbserver_t::privilege_mode()
1131 {
1132   unsigned int mode = get_field(dcsr, DCSR_PRV);
1133   if (get_field(mstatus, MSTATUS_MPRV))
1134     mode = get_field(mstatus, MSTATUS_MPP);
1135   return mode;
1136 }
1137
1138 unsigned int gdbserver_t::virtual_memory()
1139 {
1140   unsigned int mode = privilege_mode();
1141   if (mode == PRV_M)
1142     return VM_MBARE;
1143   return get_field(mstatus, MSTATUS_VM);
1144 }
1145
1146 void gdbserver_t::dr_write32(unsigned int index, uint32_t value)
1147 {
1148   sim->debug_module.ram_write32(index, value);
1149 }
1150
1151 void gdbserver_t::dr_write64(unsigned int index, uint64_t value)
1152 {
1153   dr_write32(index, value);
1154   dr_write32(index+1, value >> 32);
1155 }
1156
1157 void gdbserver_t::dr_write(enum slot slot, uint64_t value)
1158 {
1159   switch (xlen) {
1160     case 32:
1161       dr_write32(slot_offset32[slot], value);
1162       break;
1163     case 64:
1164       dr_write64(slot_offset64[slot], value);
1165       break;
1166     case 128:
1167     default:
1168       abort();
1169   }
1170 }
1171
1172 void gdbserver_t::dr_write_jump(unsigned int index)
1173 {
1174   dr_write32(index, jal(0,
1175         (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*index))));
1176 }
1177
1178 void gdbserver_t::dr_write_store(unsigned int index, unsigned int reg, enum slot slot)
1179 {
1180   assert(slot != SLOT_INST0 || index > 2);
1181   assert(slot != SLOT_DATA0 || index < 4 || index > 6);
1182   assert(slot != SLOT_DATA1 || index < 5 || index > 10);
1183   assert(slot != SLOT_DATA_LAST || index < 6 || index > 14);
1184   switch (xlen) {
1185     case 32:
1186       return dr_write32(index,
1187           sw(reg, 0, (uint16_t) DEBUG_RAM_START + 4 * slot_offset32[slot]));
1188     case 64:
1189       return dr_write32(index,
1190           sd(reg, 0, (uint16_t) DEBUG_RAM_START + 4 * slot_offset64[slot]));
1191     case 128:
1192       return dr_write32(index,
1193           sq(reg, 0, (uint16_t) DEBUG_RAM_START + 4 * slot_offset128[slot]));
1194     default:
1195       fprintf(stderr, "xlen is %d!\n", xlen);
1196       abort();
1197   }
1198 }
1199
1200 void gdbserver_t::dr_write_load(unsigned int index, unsigned int reg, enum slot slot)
1201 {
1202   switch (xlen) {
1203     case 32:
1204       return dr_write32(index,
1205           lw(reg, 0, (uint16_t) DEBUG_RAM_START + 4 * slot_offset32[slot]));
1206     case 64:
1207       return dr_write32(index,
1208           ld(reg, 0, (uint16_t) DEBUG_RAM_START + 4 * slot_offset64[slot]));
1209     case 128:
1210       return dr_write32(index,
1211           lq(reg, 0, (uint16_t) DEBUG_RAM_START + 4 * slot_offset128[slot]));
1212     default:
1213       fprintf(stderr, "xlen is %d!\n", xlen);
1214       abort();
1215   }
1216 }
1217
1218 uint32_t gdbserver_t::dr_read32(unsigned int index)
1219 {
1220   uint32_t value = sim->debug_module.ram_read32(index);
1221   D(fprintf(stderr, "read32(%d) -> 0x%x\n", index, value));
1222   return value;
1223 }
1224
1225 uint64_t gdbserver_t::dr_read64(unsigned int index)
1226 {
1227   return ((uint64_t) dr_read32(index+1) << 32) | dr_read32(index);
1228 }
1229
1230 uint64_t gdbserver_t::dr_read(enum slot slot)
1231 {
1232   switch (xlen) {
1233     case 32:
1234       return dr_read32(slot_offset32[slot]);
1235     case 64:
1236       return dr_read64(slot_offset64[slot]);
1237     case 128:
1238       abort();
1239     default:
1240       abort();
1241   }
1242 }
1243
1244 void gdbserver_t::add_operation(operation_t* operation)
1245 {
1246   operation_queue.push(operation);
1247 }
1248
1249 void gdbserver_t::accept()
1250 {
1251   client_fd = ::accept(socket_fd, NULL, NULL);
1252   if (client_fd == -1) {
1253     if (errno == EAGAIN) {
1254       // No client waiting to connect right now.
1255     } else {
1256       fprintf(stderr, "failed to accept on socket: %s (%d)\n", strerror(errno),
1257           errno);
1258       abort();
1259     }
1260   } else {
1261     fcntl(client_fd, F_SETFL, O_NONBLOCK);
1262
1263     expect_ack = false;
1264     extended_mode = false;
1265
1266     // gdb wants the core to be halted when it attaches.
1267     add_operation(new halt_op_t(*this));
1268   }
1269 }
1270
1271 void gdbserver_t::read()
1272 {
1273   // Reading from a non-blocking socket still blocks if there is no data
1274   // available.
1275
1276   size_t count = recv_buf.contiguous_empty_size();
1277   assert(count > 0);
1278   ssize_t bytes = ::read(client_fd, recv_buf.contiguous_empty(), count);
1279   if (bytes == -1) {
1280     if (errno == EAGAIN) {
1281       // We'll try again the next call.
1282     } else {
1283       fprintf(stderr, "failed to read on socket: %s (%d)\n", strerror(errno), errno);
1284       abort();
1285     }
1286   } else if (bytes == 0) {
1287     // The remote disconnected.
1288     client_fd = 0;
1289     processor_t *p = sim->get_core(0);
1290     // TODO p->set_halted(false, HR_NONE);
1291     recv_buf.reset();
1292     send_buf.reset();
1293   } else {
1294     recv_buf.data_added(bytes);
1295   }
1296 }
1297
1298 void gdbserver_t::write()
1299 {
1300   if (send_buf.empty())
1301     return;
1302
1303   while (!send_buf.empty()) {
1304     unsigned int count = send_buf.contiguous_data_size();
1305     assert(count > 0);
1306     ssize_t bytes = ::write(client_fd, send_buf.contiguous_data(), count);
1307     if (bytes == -1) {
1308       fprintf(stderr, "failed to write to socket: %s (%d)\n", strerror(errno), errno);
1309       abort();
1310     } else if (bytes == 0) {
1311       // Client can't take any more data right now.
1312       break;
1313     } else {
1314       D(fprintf(stderr, "wrote %ld bytes: ", bytes));
1315       for (unsigned int i = 0; i < bytes; i++) {
1316         D(fprintf(stderr, "%c", send_buf[i]));
1317       }
1318       D(fprintf(stderr, "\n"));
1319       send_buf.consume(bytes);
1320     }
1321   }
1322 }
1323
1324 void print_packet(const std::vector<uint8_t> &packet)
1325 {
1326   for (uint8_t c : packet) {
1327     if (c >= ' ' and c <= '~')
1328       fprintf(stderr, "%c", c);
1329     else
1330       fprintf(stderr, "\\x%02x", c);
1331   }
1332   fprintf(stderr, "\n");
1333 }
1334
1335 uint8_t compute_checksum(const std::vector<uint8_t> &packet)
1336 {
1337   uint8_t checksum = 0;
1338   for (auto i = packet.begin() + 1; i != packet.end() - 3; i++ ) {
1339     checksum += *i;
1340   }
1341   return checksum;
1342 }
1343
1344 uint8_t character_hex_value(uint8_t character)
1345 {
1346   if (character >= '0' && character <= '9')
1347     return character - '0';
1348   if (character >= 'a' && character <= 'f')
1349     return 10 + character - 'a';
1350   if (character >= 'A' && character <= 'F')
1351     return 10 + character - 'A';
1352   return 0xff;
1353 }
1354
1355 uint8_t extract_checksum(const std::vector<uint8_t> &packet)
1356 {
1357   return character_hex_value(*(packet.end() - 1)) +
1358     16 * character_hex_value(*(packet.end() - 2));
1359 }
1360
1361 void gdbserver_t::process_requests()
1362 {
1363   // See https://sourceware.org/gdb/onlinedocs/gdb/Remote-Protocol.html
1364
1365   while (!recv_buf.empty()) {
1366     std::vector<uint8_t> packet;
1367     for (unsigned int i = 0; i < recv_buf.size(); i++) {
1368       uint8_t b = recv_buf[i];
1369
1370       if (packet.empty() && expect_ack && b == '+') {
1371         recv_buf.consume(1);
1372         break;
1373       }
1374
1375       if (packet.empty() && b == 3) {
1376         D(fprintf(stderr, "Received interrupt\n"));
1377         recv_buf.consume(1);
1378         handle_interrupt();
1379         break;
1380       }
1381
1382       if (b == '$') {
1383         // Start of new packet.
1384         if (!packet.empty()) {
1385           fprintf(stderr, "Received malformed %ld-byte packet from debug client: ",
1386               packet.size());
1387           print_packet(packet);
1388           recv_buf.consume(i);
1389           break;
1390         }
1391       }
1392
1393       packet.push_back(b);
1394
1395       // Packets consist of $<packet-data>#<checksum>
1396       // where <checksum> is
1397       if (packet.size() >= 4 &&
1398           packet[packet.size()-3] == '#') {
1399         handle_packet(packet);
1400         recv_buf.consume(i+1);
1401         break;
1402       }
1403     }
1404     // There's a partial packet in the buffer. Wait until we get more data to
1405     // process it.
1406     if (packet.size()) {
1407       break;
1408     }
1409   }
1410 }
1411
1412 void gdbserver_t::handle_halt_reason(const std::vector<uint8_t> &packet)
1413 {
1414   send_packet("S00");
1415 }
1416
1417 void gdbserver_t::handle_general_registers_read(const std::vector<uint8_t> &packet)
1418 {
1419   add_operation(new general_registers_read_op_t(*this));
1420 }
1421
1422 void gdbserver_t::set_interrupt(uint32_t hartid) {
1423   sim->debug_module.set_interrupt(hartid);
1424 }
1425
1426 // First byte is the most-significant one.
1427 // Eg. "08675309" becomes 0x08675309.
1428 uint64_t consume_hex_number(std::vector<uint8_t>::const_iterator &iter,
1429     std::vector<uint8_t>::const_iterator end)
1430 {
1431   uint64_t value = 0;
1432
1433   while (iter != end) {
1434     uint8_t c = *iter;
1435     uint64_t c_value = character_hex_value(c);
1436     if (c_value > 15)
1437       break;
1438     iter++;
1439     value <<= 4;
1440     value += c_value;
1441   }
1442   return value;
1443 }
1444
1445 // First byte is the least-significant one.
1446 // Eg. "08675309" becomes 0x09536708
1447 uint64_t consume_hex_number_le(std::vector<uint8_t>::const_iterator &iter,
1448     std::vector<uint8_t>::const_iterator end)
1449 {
1450   uint64_t value = 0;
1451   unsigned int shift = 4;
1452
1453   while (iter != end) {
1454     uint8_t c = *iter;
1455     uint64_t c_value = character_hex_value(c);
1456     if (c_value > 15)
1457       break;
1458     iter++;
1459     value |= c_value << shift;
1460     if ((shift % 8) == 0)
1461       shift += 12;
1462     else
1463       shift -= 4;
1464   }
1465   return value;
1466 }
1467
1468 void consume_string(std::string &str, std::vector<uint8_t>::const_iterator &iter,
1469     std::vector<uint8_t>::const_iterator end, uint8_t separator)
1470 {
1471   while (iter != end && *iter != separator) {
1472     str.append(1, (char) *iter);
1473     iter++;
1474   }
1475 }
1476
1477 void gdbserver_t::handle_register_read(const std::vector<uint8_t> &packet)
1478 {
1479   // p n
1480
1481   std::vector<uint8_t>::const_iterator iter = packet.begin() + 2;
1482   unsigned int n = consume_hex_number(iter, packet.end());
1483   if (*iter != '#')
1484     return send_packet("E01");
1485
1486   add_operation(new register_read_op_t(*this, n));
1487 }
1488
1489 void gdbserver_t::handle_register_write(const std::vector<uint8_t> &packet)
1490 {
1491   // P n...=r...
1492
1493   std::vector<uint8_t>::const_iterator iter = packet.begin() + 2;
1494   unsigned int n = consume_hex_number(iter, packet.end());
1495   if (*iter != '=')
1496     return send_packet("E05");
1497   iter++;
1498
1499   reg_t value = consume_hex_number_le(iter, packet.end());
1500   if (*iter != '#')
1501     return send_packet("E06");
1502
1503   processor_t *p = sim->get_core(0);
1504
1505   add_operation(new register_write_op_t(*this, n, value));
1506
1507   return send_packet("OK");
1508 }
1509
1510 void gdbserver_t::handle_memory_read(const std::vector<uint8_t> &packet)
1511 {
1512   // m addr,length
1513   std::vector<uint8_t>::const_iterator iter = packet.begin() + 2;
1514   reg_t address = consume_hex_number(iter, packet.end());
1515   if (*iter != ',')
1516     return send_packet("E10");
1517   iter++;
1518   reg_t length = consume_hex_number(iter, packet.end());
1519   if (*iter != '#')
1520     return send_packet("E11");
1521
1522   add_operation(new collect_translation_info_op_t(*this, address, length));
1523   add_operation(new memory_read_op_t(*this, address, length));
1524 }
1525
1526 void gdbserver_t::handle_memory_binary_write(const std::vector<uint8_t> &packet)
1527 {
1528   // X addr,length:XX...
1529   std::vector<uint8_t>::const_iterator iter = packet.begin() + 2;
1530   reg_t address = consume_hex_number(iter, packet.end());
1531   if (*iter != ',')
1532     return send_packet("E20");
1533   iter++;
1534   reg_t length = consume_hex_number(iter, packet.end());
1535   if (*iter != ':')
1536     return send_packet("E21");
1537   iter++;
1538
1539   if (length == 0) {
1540     return send_packet("OK");
1541   }
1542
1543   unsigned char *data = new unsigned char[length];
1544   for (unsigned int i = 0; i < length; i++) {
1545     if (iter == packet.end()) {
1546       return send_packet("E22");
1547     }
1548     uint8_t c = *iter;
1549     iter++;
1550     if (c == '}') {
1551       // The binary data representation uses 7d (ascii ‘}’) as an escape
1552       // character. Any escaped byte is transmitted as the escape character
1553       // followed by the original character XORed with 0x20. For example, the
1554       // byte 0x7d would be transmitted as the two bytes 0x7d 0x5d. The bytes
1555       // 0x23 (ascii ‘#’), 0x24 (ascii ‘$’), and 0x7d (ascii ‘}’) must always
1556       // be escaped.
1557       if (iter == packet.end()) {
1558         return send_packet("E23");
1559       }
1560       c = (*iter) ^ 0x20;
1561       iter++;
1562     }
1563     data[i] = c;
1564   }
1565   if (*iter != '#')
1566     return send_packet("E4b"); // EOVERFLOW
1567
1568   add_operation(new collect_translation_info_op_t(*this, address, length));
1569   add_operation(new memory_write_op_t(*this, address, length, data));
1570 }
1571
1572 void gdbserver_t::handle_continue(const std::vector<uint8_t> &packet)
1573 {
1574   // c [addr]
1575   processor_t *p = sim->get_core(0);
1576   if (packet[2] != '#') {
1577     std::vector<uint8_t>::const_iterator iter = packet.begin() + 2;
1578     dpc = consume_hex_number(iter, packet.end());
1579     if (*iter != '#')
1580       return send_packet("E30");
1581   }
1582
1583   add_operation(new continue_op_t(*this, false));
1584 }
1585
1586 void gdbserver_t::handle_step(const std::vector<uint8_t> &packet)
1587 {
1588   // s [addr]
1589   if (packet[2] != '#') {
1590     std::vector<uint8_t>::const_iterator iter = packet.begin() + 2;
1591     die("handle_step");
1592     //p->state.pc = consume_hex_number(iter, packet.end());
1593     if (*iter != '#')
1594       return send_packet("E40");
1595   }
1596
1597   add_operation(new continue_op_t(*this, true));
1598 }
1599
1600 void gdbserver_t::handle_kill(const std::vector<uint8_t> &packet)
1601 {
1602   // k
1603   // The exact effect of this packet is not specified.
1604   // Looks like OpenOCD disconnects?
1605   // TODO
1606 }
1607
1608 void gdbserver_t::handle_extended(const std::vector<uint8_t> &packet)
1609 {
1610   // Enable extended mode. In extended mode, the remote server is made
1611   // persistent. The ‘R’ packet is used to restart the program being debugged.
1612   send_packet("OK");
1613   extended_mode = true;
1614 }
1615
1616 void gdbserver_t::handle_breakpoint(const std::vector<uint8_t> &packet)
1617 {
1618   // insert: Z type,addr,kind
1619   // remove: z type,addr,kind
1620
1621   software_breakpoint_t bp;
1622   bool insert = (packet[1] == 'Z');
1623   std::vector<uint8_t>::const_iterator iter = packet.begin() + 2;
1624   int type = consume_hex_number(iter, packet.end());
1625   if (*iter != ',')
1626     return send_packet("E50");
1627   iter++;
1628   bp.address = consume_hex_number(iter, packet.end());
1629   if (*iter != ',')
1630     return send_packet("E51");
1631   iter++;
1632   bp.size = consume_hex_number(iter, packet.end());
1633   // There may be more options after a ; here, but we don't support that.
1634   if (*iter != '#')
1635     return send_packet("E52");
1636
1637   if (type != 0) {
1638     // Only software breakpoints are supported.
1639     return send_packet("");
1640   }
1641
1642   if (bp.size != 2 && bp.size != 4) {
1643     return send_packet("E53");
1644   }
1645
1646   fence_i_required = true;
1647   add_operation(new collect_translation_info_op_t(*this, bp.address, bp.size));
1648   if (insert) {
1649     unsigned char* swbp = new unsigned char[4];
1650     if (bp.size == 2) {
1651       swbp[0] = C_EBREAK & 0xff;
1652       swbp[1] = (C_EBREAK >> 8) & 0xff;
1653     } else {
1654       swbp[0] = EBREAK & 0xff;
1655       swbp[1] = (EBREAK >> 8) & 0xff;
1656       swbp[2] = (EBREAK >> 16) & 0xff;
1657       swbp[3] = (EBREAK >> 24) & 0xff;
1658     }
1659
1660     breakpoints[bp.address] = new software_breakpoint_t(bp);
1661     add_operation(new memory_read_op_t(*this, bp.address, bp.size,
1662           breakpoints[bp.address]->instruction));
1663     add_operation(new memory_write_op_t(*this, bp.address, bp.size, swbp));
1664
1665   } else {
1666     software_breakpoint_t *found_bp;
1667     found_bp = breakpoints[bp.address];
1668     unsigned char* instruction = new unsigned char[4];
1669     memcpy(instruction, found_bp->instruction, 4);
1670     add_operation(new memory_write_op_t(*this, found_bp->address,
1671           found_bp->size, instruction));
1672     breakpoints.erase(bp.address);
1673     delete found_bp;
1674   }
1675
1676   return send_packet("OK");
1677 }
1678
1679 void gdbserver_t::handle_query(const std::vector<uint8_t> &packet)
1680 {
1681   std::string name;
1682   std::vector<uint8_t>::const_iterator iter = packet.begin() + 2;
1683
1684   consume_string(name, iter, packet.end(), ':');
1685   if (iter != packet.end())
1686     iter++;
1687   if (name == "Supported") {
1688     start_packet();
1689     while (iter != packet.end()) {
1690       std::string feature;
1691       consume_string(feature, iter, packet.end(), ';');
1692       if (iter != packet.end())
1693         iter++;
1694       if (feature == "swbreak+") {
1695         send("swbreak+;");
1696       }
1697     }
1698     send("PacketSize=131072;");
1699     return end_packet();
1700   }
1701
1702   D(fprintf(stderr, "Unsupported query %s\n", name.c_str()));
1703   return send_packet("");
1704 }
1705
1706 void gdbserver_t::handle_packet(const std::vector<uint8_t> &packet)
1707 {
1708   if (compute_checksum(packet) != extract_checksum(packet)) {
1709     fprintf(stderr, "Received %ld-byte packet with invalid checksum\n", packet.size());
1710     fprintf(stderr, "Computed checksum: %x\n", compute_checksum(packet));
1711     print_packet(packet);
1712     send("-");
1713     return;
1714   }
1715
1716   D(fprintf(stderr, "Received %ld-byte packet from debug client: ", packet.size()));
1717   D(print_packet(packet));
1718   send("+");
1719
1720   switch (packet[1]) {
1721     case '!':
1722       return handle_extended(packet);
1723     case '?':
1724       return handle_halt_reason(packet);
1725     case 'g':
1726       return handle_general_registers_read(packet);
1727 //    case 'k':
1728 //      return handle_kill(packet);
1729     case 'm':
1730       return handle_memory_read(packet);
1731 //    case 'M':
1732 //      return handle_memory_write(packet);
1733     case 'X':
1734       return handle_memory_binary_write(packet);
1735     case 'p':
1736       return handle_register_read(packet);
1737     case 'P':
1738       return handle_register_write(packet);
1739     case 'c':
1740       return handle_continue(packet);
1741     case 's':
1742       return handle_step(packet);
1743     case 'z':
1744     case 'Z':
1745       return handle_breakpoint(packet);
1746     case 'q':
1747     case 'Q':
1748       return handle_query(packet);
1749   }
1750
1751   // Not supported.
1752   D(fprintf(stderr, "** Unsupported packet: "));
1753   D(print_packet(packet));
1754   send_packet("");
1755 }
1756
1757 void gdbserver_t::handle_interrupt()
1758 {
1759   processor_t *p = sim->get_core(0);
1760   add_operation(new halt_op_t(*this, true));
1761 }
1762
1763 void gdbserver_t::handle()
1764 {
1765   if (client_fd > 0) {
1766     processor_t *p = sim->get_core(0);
1767
1768     bool interrupt = sim->debug_module.get_interrupt(0);
1769
1770     if (!interrupt && !operation_queue.empty()) {
1771       operation_t *operation = operation_queue.front();
1772       if (operation->step()) {
1773         operation_queue.pop();
1774         delete operation;
1775       }
1776     }
1777
1778     bool halt_notification = sim->debug_module.get_halt_notification(0);
1779     if (halt_notification) {
1780       sim->debug_module.clear_halt_notification(0);
1781       add_operation(new halt_op_t(*this, true));
1782     }
1783
1784     this->read();
1785     this->write();
1786
1787   } else {
1788     this->accept();
1789   }
1790
1791   if (operation_queue.empty()) {
1792     this->process_requests();
1793   }
1794 }
1795
1796 void gdbserver_t::send(const char* msg)
1797 {
1798   unsigned int length = strlen(msg);
1799   for (const char *c = msg; *c; c++)
1800     running_checksum += *c;
1801   send_buf.append((const uint8_t *) msg, length);
1802 }
1803
1804 void gdbserver_t::send(uint64_t value)
1805 {
1806   char buffer[3];
1807   for (unsigned int i = 0; i < 8; i++) {
1808     sprintf(buffer, "%02x", (int) (value & 0xff));
1809     send(buffer);
1810     value >>= 8;
1811   }
1812 }
1813
1814 void gdbserver_t::send(uint32_t value)
1815 {
1816   char buffer[3];
1817   for (unsigned int i = 0; i < 4; i++) {
1818     sprintf(buffer, "%02x", (int) (value & 0xff));
1819     send(buffer);
1820     value >>= 8;
1821   }
1822 }
1823
1824 void gdbserver_t::send_packet(const char* data)
1825 {
1826   start_packet();
1827   send(data);
1828   end_packet();
1829   expect_ack = true;
1830 }
1831
1832 void gdbserver_t::start_packet()
1833 {
1834   send("$");
1835   running_checksum = 0;
1836 }
1837
1838 void gdbserver_t::end_packet(const char* data)
1839 {
1840   if (data) {
1841     send(data);
1842   }
1843
1844   char checksum_string[4];
1845   sprintf(checksum_string, "#%02x", running_checksum);
1846   send(checksum_string);
1847   expect_ack = true;
1848 }