riscv/gdbserver.cc

   1 #include <arpa/inet.h>
   2 #include <errno.h>
   3 #include <fcntl.h>
   4 #include <stdlib.h>
   5 #include <string.h>
   6 #include <sys/socket.h>
   7 #include <sys/types.h>
   8 #include <unistd.h>
   9
  10 #include <algorithm>
  11 #include <cassert>
  12 #include <cinttypes>
  13 #include <cstdio>
  14 #include <vector>
  15
  16 #include "disasm.h"
  17 #include "sim.h"
  18 #include "gdbserver.h"
  19 #include "mmu.h"
  20
  21 #define C_EBREAK        0x9002
  22 #define EBREAK          0x00100073
  23
  24 //////////////////////////////////////// Utility Functions
  25
  26 #undef DEBUG
  27 #ifdef DEBUG
  28 #  define D(x) x
  29 #else
  30 #  define D(x)
  31 #endif // DEBUG
  32
  33 void die(const char* msg)
  34 {
  35   fprintf(stderr, "gdbserver code died: %s\n", msg);
  36   abort();
  37 }
  38
  39 // gdb's register list is defined in riscv_gdb_reg_names gdb/riscv-tdep.c in
  40 // its source tree. We must interpret the numbers the same here.
  41 enum {
  42   REG_XPR0 = 0,
  43   REG_XPR31 = 31,
  44   REG_PC = 32,
  45   REG_FPR0 = 33,
  46   REG_FPR31 = 64,
  47   REG_CSR0 = 65,
  48   REG_CSR4095 = 4160,
  49   REG_PRIV = 4161
  50 };
  51
  52 //////////////////////////////////////// Functions to generate RISC-V opcodes.
  53
  54 // TODO: Does this already exist somewhere?
  55
  56 #define ZERO    0
  57 // Using regnames.cc as source. The RVG Calling Convention of the 2.0 RISC-V
  58 // spec says it should be 2 and 3.
  59 #define S0      8
  60 #define S1      9
  61 static uint32_t bits(uint32_t value, unsigned int hi, unsigned int lo) {
  62   return (value >> lo) & ((1 << (hi+1-lo)) - 1);
  63 }
  64
  65 static uint32_t bit(uint32_t value, unsigned int b) {
  66   return (value >> b) & 1;
  67 }
  68
  69 static uint32_t jal(unsigned int rd, uint32_t imm) {
  70   return (bit(imm, 20) << 31) |
  71     (bits(imm, 10, 1) << 21) |
  72     (bit(imm, 11) << 20) |
  73     (bits(imm, 19, 12) << 12) |
  74     (rd << 7) |
  75     MATCH_JAL;
  76 }
  77
  78 static uint32_t csrsi(unsigned int csr, uint16_t imm) {
  79   return (csr << 20) |
  80     (bits(imm, 4, 0) << 15) |
  81     MATCH_CSRRSI;
  82 }
  83
  84 static uint32_t csrci(unsigned int csr, uint16_t imm) {
  85   return (csr << 20) |
  86     (bits(imm, 4, 0) << 15) |
  87     MATCH_CSRRCI;
  88 }
  89
  90 static uint32_t csrr(unsigned int rd, unsigned int csr) {
  91   return (csr << 20) | (rd << 7) | MATCH_CSRRS;
  92 }
  93
  94 static uint32_t csrw(unsigned int source, unsigned int csr) {
  95   return (csr << 20) | (source << 15) | MATCH_CSRRW;
  96 }
  97
  98 static uint32_t fence_i()
  99 {
 100   return MATCH_FENCE_I;
 101 }
 102
 103 static uint32_t sb(unsigned int src, unsigned int base, uint16_t offset)
 104 {
 105   return (bits(offset, 11, 5) << 25) |
 106     (src << 20) |
 107     (base << 15) |
 108     (bits(offset, 4, 0) << 7) |
 109     MATCH_SB;
 110 }
 111
 112 static uint32_t sh(unsigned int src, unsigned int base, uint16_t offset)
 113 {
 114   return (bits(offset, 11, 5) << 25) |
 115     (src << 20) |
 116     (base << 15) |
 117     (bits(offset, 4, 0) << 7) |
 118     MATCH_SH;
 119 }
 120
 121 static uint32_t sw(unsigned int src, unsigned int base, uint16_t offset)
 122 {
 123   return (bits(offset, 11, 5) << 25) |
 124     (src << 20) |
 125     (base << 15) |
 126     (bits(offset, 4, 0) << 7) |
 127     MATCH_SW;
 128 }
 129
 130 static uint32_t sd(unsigned int src, unsigned int base, uint16_t offset)
 131 {
 132   return (bits(offset, 11, 5) << 25) |
 133     (bits(src, 4, 0) << 20) |
 134     (base << 15) |
 135     (bits(offset, 4, 0) << 7) |
 136     MATCH_SD;
 137 }
 138
 139 static uint32_t sq(unsigned int src, unsigned int base, uint16_t offset)
 140 {
 141 #if 0
 142   return (bits(offset, 11, 5) << 25) |
 143     (bits(src, 4, 0) << 20) |
 144     (base << 15) |
 145     (bits(offset, 4, 0) << 7) |
 146     MATCH_SQ;
 147 #else
 148   abort();
 149 #endif
 150 }
 151
 152 static uint32_t lq(unsigned int rd, unsigned int base, uint16_t offset)
 153 {
 154 #if 0
 155   return (bits(offset, 11, 0) << 20) |
 156     (base << 15) |
 157     (bits(rd, 4, 0) << 7) |
 158     MATCH_LQ;
 159 #else
 160   abort();
 161 #endif
 162 }
 163
 164 static uint32_t ld(unsigned int rd, unsigned int base, uint16_t offset)
 165 {
 166   return (bits(offset, 11, 0) << 20) |
 167     (base << 15) |
 168     (bits(rd, 4, 0) << 7) |
 169     MATCH_LD;
 170 }
 171
 172 static uint32_t lw(unsigned int rd, unsigned int base, uint16_t offset)
 173 {
 174   return (bits(offset, 11, 0) << 20) |
 175     (base << 15) |
 176     (bits(rd, 4, 0) << 7) |
 177     MATCH_LW;
 178 }
 179
 180 static uint32_t lh(unsigned int rd, unsigned int base, uint16_t offset)
 181 {
 182   return (bits(offset, 11, 0) << 20) |
 183     (base << 15) |
 184     (bits(rd, 4, 0) << 7) |
 185     MATCH_LH;
 186 }
 187
 188 static uint32_t lb(unsigned int rd, unsigned int base, uint16_t offset)
 189 {
 190   return (bits(offset, 11, 0) << 20) |
 191     (base << 15) |
 192     (bits(rd, 4, 0) << 7) |
 193     MATCH_LB;
 194 }
 195
 196 static uint32_t fsw(unsigned int src, unsigned int base, uint16_t offset)
 197 {
 198   return (bits(offset, 11, 5) << 25) |
 199     (bits(src, 4, 0) << 20) |
 200     (base << 15) |
 201     (bits(offset, 4, 0) << 7) |
 202     MATCH_FSW;
 203 }
 204
 205 static uint32_t fsd(unsigned int src, unsigned int base, uint16_t offset)
 206 {
 207   return (bits(offset, 11, 5) << 25) |
 208     (bits(src, 4, 0) << 20) |
 209     (base << 15) |
 210     (bits(offset, 4, 0) << 7) |
 211     MATCH_FSD;
 212 }
 213
 214 static uint32_t flw(unsigned int src, unsigned int base, uint16_t offset)
 215 {
 216   return (bits(offset, 11, 5) << 25) |
 217     (bits(src, 4, 0) << 20) |
 218     (base << 15) |
 219     (bits(offset, 4, 0) << 7) |
 220     MATCH_FLW;
 221 }
 222
 223 static uint32_t fld(unsigned int src, unsigned int base, uint16_t offset)
 224 {
 225   return (bits(offset, 11, 5) << 25) |
 226     (bits(src, 4, 0) << 20) |
 227     (base << 15) |
 228     (bits(offset, 4, 0) << 7) |
 229     MATCH_FLD;
 230 }
 231
 232 static uint32_t addi(unsigned int dest, unsigned int src, uint16_t imm)
 233 {
 234   return (bits(imm, 11, 0) << 20) |
 235     (src << 15) |
 236     (dest << 7) |
 237     MATCH_ADDI;
 238 }
 239
 240 static uint32_t ori(unsigned int dest, unsigned int src, uint16_t imm)
 241 {
 242   return (bits(imm, 11, 0) << 20) |
 243     (src << 15) |
 244     (dest << 7) |
 245     MATCH_ORI;
 246 }
 247
 248 static uint32_t xori(unsigned int dest, unsigned int src, uint16_t imm)
 249 {
 250   return (bits(imm, 11, 0) << 20) |
 251     (src << 15) |
 252     (dest << 7) |
 253     MATCH_XORI;
 254 }
 255
 256 static uint32_t srli(unsigned int dest, unsigned int src, uint8_t shamt)
 257 {
 258   return (bits(shamt, 4, 0) << 20) |
 259     (src << 15) |
 260     (dest << 7) |
 261     MATCH_SRLI;
 262 }
 263
 264
 265 static uint32_t nop()
 266 {
 267   return addi(0, 0, 0);
 268 }
 269
 270 template <typename T>
 271 unsigned int circular_buffer_t<T>::size() const
 272 {
 273   if (end >= start)
 274     return end - start;
 275   else
 276     return end + capacity - start;
 277 }
 278
 279 template <typename T>
 280 void circular_buffer_t<T>::consume(unsigned int bytes)
 281 {
 282   start = (start + bytes) % capacity;
 283 }
 284
 285 template <typename T>
 286 unsigned int circular_buffer_t<T>::contiguous_empty_size() const
 287 {
 288   if (end >= start)
 289     if (start == 0)
 290       return capacity - end - 1;
 291     else
 292       return capacity - end;
 293   else
 294     return start - end - 1;
 295 }
 296
 297 template <typename T>
 298 unsigned int circular_buffer_t<T>::contiguous_data_size() const
 299 {
 300   if (end >= start)
 301     return end - start;
 302   else
 303     return capacity - start;
 304 }
 305
 306 template <typename T>
 307 void circular_buffer_t<T>::data_added(unsigned int bytes)
 308 {
 309   end += bytes;
 310   assert(end <= capacity);
 311   if (end == capacity)
 312     end = 0;
 313 }
 314
 315 template <typename T>
 316 void circular_buffer_t<T>::reset()
 317 {
 318   start = 0;
 319   end = 0;
 320 }
 321
 322 template <typename T>
 323 void circular_buffer_t<T>::append(const T *src, unsigned int count)
 324 {
 325   unsigned int copy = std::min(count, contiguous_empty_size());
 326   memcpy(contiguous_empty(), src, copy * sizeof(T));
 327   data_added(copy);
 328   count -= copy;
 329   if (count > 0) {
 330     assert(count < contiguous_empty_size());
 331     memcpy(contiguous_empty(), src, count * sizeof(T));
 332     data_added(count);
 333   }
 334 }
 335
 336 ////////////////////////////// Debug Operations
 337
 338 class halt_op_t : public operation_t
 339 {
 340   public:
 341     halt_op_t(gdbserver_t& gdbserver, bool send_status=false) :
 342       operation_t(gdbserver), send_status(send_status),
 343       state(ST_ENTER) {};
 344
 345     void write_dpc_program() {
 346       gs.dr_write32(0, csrsi(CSR_DCSR, DCSR_HALT));
 347       gs.dr_write32(1, csrr(S0, CSR_DPC));
 348       gs.dr_write_store(2, S0, SLOT_DATA0);
 349       gs.dr_write_jump(3);
 350       gs.set_interrupt(0);
 351     }
 352
 353     bool perform_step(unsigned int step) {
 354       switch (state) {
 355         gs.tselect_valid = false;
 356         case ST_ENTER:
 357           if (gs.xlen == 0) {
 358             gs.dr_write32(0, xori(S1, ZERO, -1));
 359             gs.dr_write32(1, srli(S1, S1, 31));
 360             // 0x00000001  0x00000001:ffffffff  0x00000001:ffffffff:ffffffff:ffffffff
 361             gs.dr_write32(2, sw(S1, ZERO, DEBUG_RAM_START));
 362             gs.dr_write32(3, srli(S1, S1, 31));
 363             // 0x00000000  0x00000000:00000003  0x00000000:00000003:ffffffff:ffffffff
 364             gs.dr_write32(4, sw(S1, ZERO, DEBUG_RAM_START + 4));
 365             gs.dr_write_jump(5);
 366             gs.set_interrupt(0);
 367             state = ST_XLEN;
 368
 369           } else {
 370             write_dpc_program();
 371             state = ST_DPC;
 372           }
 373           return false;
 374
 375         case ST_XLEN:
 376           {
 377             uint32_t word0 = gs.dr_read32(0);
 378             uint32_t word1 = gs.dr_read32(1);
 379
 380             if (word0 == 1 && word1 == 0) {
 381               gs.xlen = 32;
 382             } else if (word0 == 0xffffffff && word1 == 3) {
 383               gs.xlen = 64;
 384             } else if (word0 == 0xffffffff && word1 == 0xffffffff) {
 385               gs.xlen = 128;
 386             }
 387
 388             write_dpc_program();
 389             state = ST_DPC;
 390             return false;
 391           }
 392
 393         case ST_DPC:
 394           gs.dpc = gs.dr_read(SLOT_DATA0);
 395           gs.dr_write32(0, csrr(S0, CSR_MSTATUS));
 396           gs.dr_write_store(1, S0, SLOT_DATA0);
 397           gs.dr_write_jump(2);
 398           gs.set_interrupt(0);
 399           state = ST_MSTATUS;
 400           return false;
 401
 402         case ST_MSTATUS:
 403           gs.mstatus = gs.dr_read(SLOT_DATA0);
 404           gs.dr_write32(0, csrr(S0, CSR_DCSR));
 405           gs.dr_write32(1, sw(S0, 0, (uint16_t) DEBUG_RAM_START + 16));
 406           gs.dr_write_jump(2);
 407           gs.set_interrupt(0);
 408           state = ST_DCSR;
 409           return false;
 410
 411         case ST_DCSR:
 412           gs.dcsr = gs.dr_read32(4);
 413
 414           gs.sptbr_valid = false;
 415           gs.pte_cache.clear();
 416
 417           if (send_status) {
 418             switch (get_field(gs.dcsr, DCSR_CAUSE)) {
 419               case DCSR_CAUSE_NONE:
 420                 fprintf(stderr, "Internal error. Processor halted without reason.\n");
 421                 abort();
 422
 423               case DCSR_CAUSE_DEBUGINT:
 424                 gs.send_packet("S02");   // Pretend program received SIGINT.
 425                 break;
 426
 427               case DCSR_CAUSE_HWBP:
 428               case DCSR_CAUSE_STEP:
 429               case DCSR_CAUSE_HALT:
 430                 // There's no gdb code for this.
 431                 gs.send_packet("T05");
 432                 break;
 433               case DCSR_CAUSE_SWBP:
 434                 gs.send_packet("T05swbreak:;");
 435                 break;
 436             }
 437           }
 438           return true;
 439
 440         default:
 441           assert(0);
 442       }
 443     }
 444
 445   private:
 446     bool send_status;
 447     enum {
 448       ST_ENTER,
 449       ST_XLEN,
 450       ST_DPC,
 451       ST_MSTATUS,
 452       ST_DCSR
 453     } state;
 454 };
 455
 456 class continue_op_t : public operation_t
 457 {
 458   public:
 459     continue_op_t(gdbserver_t& gdbserver, bool single_step) :
 460       operation_t(gdbserver), single_step(single_step) {};
 461
 462     bool perform_step(unsigned int step) {
 463       D(fprintf(stderr, "continue step %d\n", step));
 464       switch (step) {
 465         case 0:
 466           gs.dr_write_load(0, S0, SLOT_DATA0);
 467           gs.dr_write32(1, csrw(S0, CSR_DPC));
 468           // TODO: Isn't there a fence.i in Debug ROM already?
 469           if (gs.fence_i_required) {
 470             gs.dr_write32(2, fence_i());
 471             gs.dr_write_jump(3);
 472             gs.fence_i_required = false;
 473           } else {
 474             gs.dr_write_jump(2);
 475           }
 476           gs.dr_write(SLOT_DATA0, gs.dpc);
 477           gs.set_interrupt(0);
 478           return false;
 479
 480         case 1:
 481           gs.dr_write_load(0, S0, SLOT_DATA0);
 482           gs.dr_write32(1, csrw(S0, CSR_MSTATUS));
 483           gs.dr_write_jump(2);
 484           gs.dr_write(SLOT_DATA0, gs.mstatus);
 485           gs.set_interrupt(0);
 486           return false;
 487
 488         case 2:
 489           gs.dr_write32(0, lw(S0, 0, (uint16_t) DEBUG_RAM_START+16));
 490           gs.dr_write32(1, csrw(S0, CSR_DCSR));
 491           gs.dr_write_jump(2);
 492
 493           reg_t dcsr = set_field(gs.dcsr, DCSR_HALT, 0);
 494           dcsr = set_field(dcsr, DCSR_STEP, single_step);
 495           // Software breakpoints should go here.
 496           dcsr = set_field(dcsr, DCSR_EBREAKM, 1);
 497           dcsr = set_field(dcsr, DCSR_EBREAKH, 1);
 498           dcsr = set_field(dcsr, DCSR_EBREAKS, 1);
 499           dcsr = set_field(dcsr, DCSR_EBREAKU, 1);
 500           gs.dr_write32(4, dcsr);
 501
 502           gs.set_interrupt(0);
 503           return true;
 504       }
 505       return false;
 506     }
 507
 508   private:
 509     bool single_step;
 510 };
 511
 512 class general_registers_read_op_t : public operation_t
 513 {
 514   // Register order that gdb expects is:
 515   //   "x0",  "x1",  "x2",  "x3",  "x4",  "x5",  "x6",  "x7",
 516   //   "x8",  "x9",  "x10", "x11", "x12", "x13", "x14", "x15",
 517   //   "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23",
 518   //   "x24", "x25", "x26", "x27", "x28", "x29", "x30", "x31",
 519
 520   // Each byte of register data is described by two hex digits. The bytes with
 521   // the register are transmitted in target byte order. The size of each
 522   // register and their position within the ‘g’ packet are determined by the
 523   // gdb internal gdbarch functions DEPRECATED_REGISTER_RAW_SIZE and
 524   // gdbarch_register_name.
 525
 526   public:
 527     general_registers_read_op_t(gdbserver_t& gdbserver) :
 528       operation_t(gdbserver) {};
 529
 530     bool perform_step(unsigned int step)
 531     {
 532       D(fprintf(stderr, "register_read step %d\n", step));
 533       if (step == 0) {
 534         gs.start_packet();
 535
 536         // x0 is always zero.
 537         if (gs.xlen == 32) {
 538           gs.send((uint32_t) 0);
 539         } else {
 540           gs.send((uint64_t) 0);
 541         }
 542
 543         gs.dr_write_store(0, 1, SLOT_DATA0);
 544         gs.dr_write_store(1, 2, SLOT_DATA1);
 545         gs.dr_write_jump(2);
 546         gs.set_interrupt(0);
 547         return false;
 548       }
 549
 550       if (gs.xlen == 32) {
 551         gs.send((uint32_t) gs.dr_read(SLOT_DATA0));
 552       } else {
 553         gs.send((uint64_t) gs.dr_read(SLOT_DATA0));
 554       }
 555       if (step >= 16) {
 556         gs.end_packet();
 557         return true;
 558       }
 559
 560       if (gs.xlen == 32) {
 561         gs.send((uint32_t) gs.dr_read(SLOT_DATA1));
 562       } else {
 563         gs.send((uint64_t) gs.dr_read(SLOT_DATA1));
 564       }
 565
 566       unsigned int current_reg = 2 * step + 1;
 567       unsigned int i = 0;
 568       if (current_reg == S1) {
 569         gs.dr_write_load(i++, S1, SLOT_DATA_LAST);
 570       }
 571       gs.dr_write_store(i++, current_reg, SLOT_DATA0);
 572       if (current_reg + 1 == S0) {
 573         gs.dr_write32(i++, csrr(S0, CSR_DSCRATCH));
 574       }
 575       if (step < 15) {
 576         gs.dr_write_store(i++, current_reg+1, SLOT_DATA1);
 577       }
 578       gs.dr_write_jump(i);
 579       gs.set_interrupt(0);
 580
 581       return false;
 582     }
 583 };
 584
 585 class register_read_op_t : public operation_t
 586 {
 587   public:
 588     register_read_op_t(gdbserver_t& gdbserver, unsigned int reg) :
 589       operation_t(gdbserver), reg(reg) {};
 590
 591     bool perform_step(unsigned int step)
 592     {
 593       switch (step) {
 594         case 0:
 595           if (reg >= REG_XPR0 && reg <= REG_XPR31) {
 596             die("handle_register_read");
 597             // send(p->state.XPR[reg - REG_XPR0]);
 598           } else if (reg == REG_PC) {
 599             gs.start_packet();
 600             if (gs.xlen == 32) {
 601               gs.send((uint32_t) gs.dpc);
 602             } else {
 603               gs.send(gs.dpc);
 604             }
 605             gs.end_packet();
 606             return true;
 607           } else if (reg >= REG_FPR0 && reg <= REG_FPR31) {
 608             // send(p->state.FPR[reg - REG_FPR0]);
 609             if (gs.xlen == 32) {
 610               gs.dr_write32(0, fsw(reg - REG_FPR0, 0, (uint16_t) DEBUG_RAM_START + 16));
 611             } else {
 612               gs.dr_write32(0, fsd(reg - REG_FPR0, 0, (uint16_t) DEBUG_RAM_START + 16));
 613             }
 614             gs.dr_write_jump(1);
 615           } else if (reg >= REG_CSR0 && reg <= REG_CSR4095) {
 616             gs.dr_write32(0, csrr(S0, reg - REG_CSR0));
 617             gs.dr_write_store(1, S0, SLOT_DATA0);
 618             gs.dr_write_jump(2);
 619             // If we hit an exception reading the CSR, we'll end up returning ~0 as
 620             // the register's value, which is what we want. (Right?)
 621             gs.dr_write(SLOT_DATA0, ~(uint64_t) 0);
 622           } else if (reg == REG_PRIV) {
 623             gs.start_packet();
 624             gs.send((uint8_t) get_field(gs.dcsr, DCSR_PRV));
 625             gs.end_packet();
 626             return true;
 627           } else {
 628             gs.send_packet("E02");
 629             return true;
 630           }
 631           gs.set_interrupt(0);
 632           return false;
 633
 634         case 1:
 635           gs.start_packet();
 636           if (gs.xlen == 32) {
 637             gs.send(gs.dr_read32(4));
 638           } else {
 639             gs.send(gs.dr_read(SLOT_DATA0));
 640           }
 641           gs.end_packet();
 642           return true;
 643       }
 644       return false;
 645     }
 646
 647   private:
 648     unsigned int reg;
 649 };
 650
 651 class register_write_op_t : public operation_t
 652 {
 653   public:
 654     register_write_op_t(gdbserver_t& gdbserver, unsigned int reg, reg_t value) :
 655       operation_t(gdbserver), reg(reg), value(value) {};
 656
 657     bool perform_step(unsigned int step)
 658     {
 659       gs.dr_write_load(0, S0, SLOT_DATA0);
 660       gs.dr_write(SLOT_DATA0, value);
 661       if (reg == S0) {
 662         gs.dr_write32(1, csrw(S0, CSR_DSCRATCH));
 663         gs.dr_write_jump(2);
 664       } else if (reg == S1) {
 665         gs.dr_write_store(1, S0, SLOT_DATA_LAST);
 666         gs.dr_write_jump(2);
 667       } else if (reg >= REG_XPR0 && reg <= REG_XPR31) {
 668         gs.dr_write32(1, addi(reg, S0, 0));
 669         gs.dr_write_jump(2);
 670       } else if (reg == REG_PC) {
 671         gs.dpc = value;
 672         return true;
 673       } else if (reg >= REG_FPR0 && reg <= REG_FPR31) {
 674         if (gs.xlen == 32) {
 675           gs.dr_write32(0, flw(reg - REG_FPR0, 0, (uint16_t) DEBUG_RAM_START + 16));
 676         } else {
 677           gs.dr_write32(0, fld(reg - REG_FPR0, 0, (uint16_t) DEBUG_RAM_START + 16));
 678         }
 679         gs.dr_write_jump(1);
 680       } else if (reg >= REG_CSR0 && reg <= REG_CSR4095) {
 681         gs.dr_write32(1, csrw(S0, reg - REG_CSR0));
 682         gs.dr_write_jump(2);
 683         if (reg == REG_CSR0 + CSR_SPTBR) {
 684           gs.sptbr = value;
 685           gs.sptbr_valid = true;
 686         }
 687       } else if (reg == REG_PRIV) {
 688         gs.dcsr = set_field(gs.dcsr, DCSR_PRV, value);
 689         return true;
 690       } else {
 691         gs.send_packet("E02");
 692         return true;
 693       }
 694       gs.set_interrupt(0);
 695       gs.send_packet("OK");
 696       return true;
 697     }
 698
 699   private:
 700     unsigned int reg;
 701     reg_t value;
 702 };
 703
 704 class memory_read_op_t : public operation_t
 705 {
 706   public:
 707     // Read length bytes from vaddr, storing the result into data.
 708     // If data is NULL, send the result straight to gdb.
 709     memory_read_op_t(gdbserver_t& gdbserver, reg_t vaddr, unsigned int length,
 710         unsigned char *data=NULL) :
 711       operation_t(gdbserver), vaddr(vaddr), length(length), data(data) {};
 712
 713     bool perform_step(unsigned int step)
 714     {
 715       if (step == 0) {
 716         // address goes in S0
 717         paddr = gs.translate(vaddr);
 718         access_size = gs.find_access_size(paddr, length);
 719
 720         gs.dr_write_load(0, S0, SLOT_DATA0);
 721         switch (access_size) {
 722           case 1:
 723             gs.dr_write32(1, lb(S1, S0, 0));
 724             break;
 725           case 2:
 726             gs.dr_write32(1, lh(S1, S0, 0));
 727             break;
 728           case 4:
 729             gs.dr_write32(1, lw(S1, S0, 0));
 730             break;
 731           case 8:
 732             gs.dr_write32(1, ld(S1, S0, 0));
 733             break;
 734         }
 735         gs.dr_write_store(2, S1, SLOT_DATA1);
 736         gs.dr_write_jump(3);
 737         gs.dr_write(SLOT_DATA0, paddr);
 738         gs.set_interrupt(0);
 739
 740         if (!data) {
 741           gs.start_packet();
 742         }
 743         return false;
 744       }
 745
 746       char buffer[3];
 747       reg_t value = gs.dr_read(SLOT_DATA1);
 748       for (unsigned int i = 0; i < access_size; i++) {
 749         if (data) {
 750           *(data++) = value & 0xff;
 751           D(fprintf(stderr, "%02x", (unsigned int) (value & 0xff)));
 752         } else {
 753           sprintf(buffer, "%02x", (unsigned int) (value & 0xff));
 754           gs.send(buffer);
 755         }
 756         value >>= 8;
 757       }
 758       if (data) {
 759         D(fprintf(stderr, "\n"));
 760       }
 761       length -= access_size;
 762       paddr += access_size;
 763
 764       if (length == 0) {
 765         if (!data) {
 766           gs.end_packet();
 767         }
 768         return true;
 769       } else {
 770         gs.dr_write(SLOT_DATA0, paddr);
 771         gs.set_interrupt(0);
 772         return false;
 773       }
 774     }
 775
 776   private:
 777     reg_t vaddr;
 778     unsigned int length;
 779     unsigned char* data;
 780     reg_t paddr;
 781     unsigned int access_size;
 782 };
 783
 784 class memory_write_op_t : public operation_t
 785 {
 786   public:
 787     memory_write_op_t(gdbserver_t& gdbserver, reg_t vaddr, unsigned int length,
 788         const unsigned char *data) :
 789       operation_t(gdbserver), vaddr(vaddr), offset(0), length(length), data(data) {};
 790
 791     ~memory_write_op_t() {
 792       delete[] data;
 793     }
 794
 795     bool perform_step(unsigned int step)
 796     {
 797       reg_t paddr = gs.translate(vaddr);
 798
 799       unsigned int data_offset;
 800       switch (gs.xlen) {
 801         case 32:
 802           data_offset = slot_offset32[SLOT_DATA1];
 803           break;
 804         case 64:
 805           data_offset = slot_offset64[SLOT_DATA1];
 806           break;
 807         case 128:
 808           data_offset = slot_offset128[SLOT_DATA1];
 809           break;
 810         default:
 811           abort();
 812       }
 813
 814       if (step == 0) {
 815         access_size = gs.find_access_size(paddr, length);
 816
 817         D(fprintf(stderr, "write to 0x%lx -> 0x%lx (access=%d): ", vaddr, paddr,
 818             access_size));
 819         for (unsigned int i = 0; i < length; i++) {
 820           D(fprintf(stderr, "%02x", data[i]));
 821         }
 822         D(fprintf(stderr, "\n"));
 823
 824         // address goes in S0
 825         gs.dr_write_load(0, S0, SLOT_DATA0);
 826         switch (access_size) {
 827           case 1:
 828             gs.dr_write32(1, lb(S1, 0, (uint16_t) DEBUG_RAM_START + 4*data_offset));
 829             gs.dr_write32(2, sb(S1, S0, 0));
 830             gs.dr_write32(data_offset, data[0]);
 831             break;
 832           case 2:
 833             gs.dr_write32(1, lh(S1, 0, (uint16_t) DEBUG_RAM_START + 4*data_offset));
 834             gs.dr_write32(2, sh(S1, S0, 0));
 835             gs.dr_write32(data_offset, data[0] | (data[1] << 8));
 836             break;
 837           case 4:
 838             gs.dr_write32(1, lw(S1, 0, (uint16_t) DEBUG_RAM_START + 4*data_offset));
 839             gs.dr_write32(2, sw(S1, S0, 0));
 840             gs.dr_write32(data_offset, data[0] | (data[1] << 8) |
 841                 (data[2] << 16) | (data[3] << 24));
 842             break;
 843           case 8:
 844             gs.dr_write32(1, ld(S1, 0, (uint16_t) DEBUG_RAM_START + 4*data_offset));
 845             gs.dr_write32(2, sd(S1, S0, 0));
 846             gs.dr_write32(data_offset, data[0] | (data[1] << 8) |
 847                 (data[2] << 16) | (data[3] << 24));
 848             gs.dr_write32(data_offset+1, data[4] | (data[5] << 8) |
 849                 (data[6] << 16) | (data[7] << 24));
 850             break;
 851           default:
 852             fprintf(stderr, "gdbserver error: write %d bytes to 0x%016" PRIx64
 853                     " -> 0x%016" PRIx64 "; access_size=%d\n",
 854                     length, vaddr, paddr, access_size);
 855             gs.send_packet("E12");
 856             return true;
 857         }
 858         gs.dr_write_jump(3);
 859         gs.dr_write(SLOT_DATA0, paddr);
 860         gs.set_interrupt(0);
 861
 862         return false;
 863       }
 864
 865       if (gs.dr_read32(DEBUG_RAM_SIZE / 4 - 1)) {
 866         fprintf(stderr, "Exception happened while writing to 0x%016" PRIx64
 867                 " -> 0x%016" PRIx64 "\n", vaddr, paddr);
 868       }
 869
 870       offset += access_size;
 871       if (offset >= length) {
 872         gs.send_packet("OK");
 873         return true;
 874       } else {
 875         const unsigned char *d = data + offset;
 876         switch (access_size) {
 877           case 1:
 878             gs.dr_write32(data_offset, d[0]);
 879             break;
 880           case 2:
 881             gs.dr_write32(data_offset, d[0] | (d[1] << 8));
 882             break;
 883           case 4:
 884             gs.dr_write32(data_offset, d[0] | (d[1] << 8) |
 885                 (d[2] << 16) | (d[3] << 24));
 886             break;
 887           case 8:
 888             gs.dr_write32(data_offset, d[0] | (d[1] << 8) |
 889                 (d[2] << 16) | (d[3] << 24));
 890             gs.dr_write32(data_offset+1, d[4] | (d[5] << 8) |
 891                 (d[6] << 16) | (d[7] << 24));
 892             break;
 893           default:
 894             gs.send_packet("E13");
 895             return true;
 896         }
 897         gs.dr_write(SLOT_DATA0, paddr + offset);
 898         gs.set_interrupt(0);
 899         return false;
 900       }
 901     }
 902
 903   private:
 904     reg_t vaddr;
 905     unsigned int offset;
 906     unsigned int length;
 907     unsigned int access_size;
 908     const unsigned char *data;
 909 };
 910
 911 class collect_translation_info_op_t : public operation_t
 912 {
 913   public:
 914     // Read sufficient information from the target into gdbserver structures so
 915     // that it's possible to translate vaddr, vaddr+length, and all addresses
 916     // in between to physical addresses.
 917     collect_translation_info_op_t(gdbserver_t& gdbserver, reg_t vaddr, size_t length) :
 918       operation_t(gdbserver), state(STATE_START), vaddr(vaddr), length(length) {};
 919
 920     bool perform_step(unsigned int step)
 921     {
 922       unsigned int vm = gs.virtual_memory();
 923
 924       if (step == 0) {
 925         switch (vm) {
 926           case VM_MBARE:
 927             // Nothing to be done.
 928             return true;
 929
 930           case VM_SV32:
 931             levels = 2;
 932             ptidxbits = 10;
 933             ptesize = 4;
 934             break;
 935           case VM_SV39:
 936             levels = 3;
 937             ptidxbits = 9;
 938             ptesize = 8;
 939             break;
 940           case VM_SV48:
 941             levels = 4;
 942             ptidxbits = 9;
 943             ptesize = 8;
 944             break;
 945
 946           default:
 947             {
 948               char buf[100];
 949               sprintf(buf, "VM mode %d is not supported by gdbserver.cc.", vm);
 950               die(buf);
 951               return true;        // die doesn't return, but gcc doesn't know that.
 952             }
 953         }
 954       }
 955
 956       // Perform any reads from the just-completed action.
 957       switch (state) {
 958         case STATE_START:
 959           break;
 960         case STATE_READ_SPTBR:
 961           gs.sptbr = gs.dr_read(SLOT_DATA0);
 962           gs.sptbr_valid = true;
 963           break;
 964         case STATE_READ_PTE:
 965           if (ptesize == 4) {
 966               gs.pte_cache[pte_addr] = gs.dr_read32(4);
 967           } else {
 968               gs.pte_cache[pte_addr] = ((uint64_t) gs.dr_read32(5) << 32) |
 969                   gs.dr_read32(4);
 970           }
 971           D(fprintf(stderr, "pte_cache[0x%lx] = 0x%lx\n", pte_addr, gs.pte_cache[pte_addr]));
 972           break;
 973       }
 974
 975       // Set up the next action.
 976       // We only get here for VM_SV32/39/38.
 977
 978       if (!gs.sptbr_valid) {
 979         state = STATE_READ_SPTBR;
 980         gs.dr_write32(0, csrr(S0, CSR_SPTBR));
 981         gs.dr_write_store(1, S0, SLOT_DATA0);
 982         gs.dr_write_jump(2);
 983         gs.set_interrupt(0);
 984         return false;
 985       }
 986
 987       reg_t base = gs.sptbr << PGSHIFT;
 988       int ptshift = (levels - 1) * ptidxbits;
 989       for (unsigned int i = 0; i < levels; i++, ptshift -= ptidxbits) {
 990         reg_t idx = (vaddr >> (PGSHIFT + ptshift)) & ((1 << ptidxbits) - 1);
 991
 992         pte_addr = base + idx * ptesize;
 993         auto it = gs.pte_cache.find(pte_addr);
 994         if (it == gs.pte_cache.end()) {
 995           state = STATE_READ_PTE;
 996           if (ptesize == 4) {
 997             gs.dr_write32(0, lw(S0, 0, (uint16_t) DEBUG_RAM_START + 16));
 998             gs.dr_write32(1, lw(S1, S0, 0));
 999             gs.dr_write32(2, sw(S1, 0, (uint16_t) DEBUG_RAM_START + 16));
1000           } else {
1001             assert(gs.xlen >= 64);
1002             gs.dr_write32(0, ld(S0, 0, (uint16_t) DEBUG_RAM_START + 16));
1003             gs.dr_write32(1, ld(S1, S0, 0));
1004             gs.dr_write32(2, sd(S1, 0, (uint16_t) DEBUG_RAM_START + 16));
1005           }
1006           gs.dr_write32(3, jal(0, (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*3))));
1007           gs.dr_write32(4, pte_addr);
1008           gs.dr_write32(5, pte_addr >> 32);
1009           gs.set_interrupt(0);
1010           return false;
1011         }
1012
1013         reg_t pte = gs.pte_cache[pte_addr];
1014         reg_t ppn = pte >> PTE_PPN_SHIFT;
1015
1016         if (PTE_TABLE(pte)) { // next level of page table
1017           base = ppn << PGSHIFT;
1018         } else {
1019           // We've collected all the data required for the translation.
1020           return true;
1021         }
1022       }
1023       fprintf(stderr,
1024           "ERROR: gdbserver couldn't find appropriate PTEs to translate 0x%016" PRIx64 "\n",
1025           vaddr);
1026       return true;
1027     }
1028
1029   private:
1030     enum {
1031       STATE_START,
1032       STATE_READ_SPTBR,
1033       STATE_READ_PTE
1034     } state;
1035     reg_t vaddr;
1036     size_t length;
1037     unsigned int levels;
1038     unsigned int ptidxbits;
1039     unsigned int ptesize;
1040     reg_t pte_addr;
1041 };
1042
1043 class hardware_breakpoint_insert_op_t : public operation_t
1044 {
1045   public:
1046     hardware_breakpoint_insert_op_t(gdbserver_t& gdbserver,
1047         hardware_breakpoint_t bp) :
1048       operation_t(gdbserver), state(STATE_START), bp(bp) {};
1049
1050     void write_new_index_program()
1051     {
1052       gs.dr_write_load(0, S0, SLOT_DATA1);
1053       gs.dr_write32(1, csrw(S0, CSR_TSELECT));
1054       gs.dr_write32(2, csrr(S0, CSR_TSELECT));
1055       gs.dr_write_store(3, S0, SLOT_DATA1);
1056       gs.dr_write_jump(4);
1057       gs.dr_write(SLOT_DATA1, bp.index);
1058     }
1059
1060     bool perform_step(unsigned int step)
1061     {
1062       switch (state) {
1063         case STATE_START:
1064           bp.index = 0;
1065           write_new_index_program();
1066           state = STATE_CHECK_INDEX;
1067           break;
1068
1069         case STATE_CHECK_INDEX:
1070           if (gs.dr_read(SLOT_DATA1) != bp.index) {
1071             // We've exhausted breakpoints without finding an appropriate one.
1072             gs.send_packet("E58");
1073             return true;
1074           }
1075
1076           gs.dr_write32(0, csrr(S0, CSR_TDATA1));
1077           gs.dr_write_store(1, S0, SLOT_DATA0);
1078           gs.dr_write_jump(2);
1079           state = STATE_CHECK_MCONTROL;
1080           break;
1081
1082         case STATE_CHECK_MCONTROL:
1083           {
1084             reg_t mcontrol = gs.dr_read(SLOT_DATA0);
1085             unsigned int type = mcontrol >> (gs.xlen - 4);
1086             if (type == 0) {
1087               // We've exhausted breakpoints without finding an appropriate one.
1088               gs.send_packet("E58");
1089               return true;
1090             }
1091
1092             if (type == 2 &&
1093                 !get_field(mcontrol, MCONTROL_EXECUTE) &&
1094                 !get_field(mcontrol, MCONTROL_LOAD) &&
1095                 !get_field(mcontrol, MCONTROL_STORE)) {
1096               // Found an unused trigger.
1097               gs.dr_write_load(0, S0, SLOT_DATA1);
1098               gs.dr_write32(1, csrw(S0, CSR_TDATA1));
1099               gs.dr_write_jump(2);
1100               mcontrol = set_field(0, MCONTROL_ACTION, MCONTROL_ACTION_DEBUG_MODE);
1101               mcontrol = set_field(mcontrol, MCONTROL_DMODE(gs.xlen), 1);
1102               mcontrol = set_field(mcontrol, MCONTROL_MATCH, MCONTROL_MATCH_EQUAL);
1103               mcontrol = set_field(mcontrol, MCONTROL_M, 1);
1104               mcontrol = set_field(mcontrol, MCONTROL_H, 1);
1105               mcontrol = set_field(mcontrol, MCONTROL_S, 1);
1106               mcontrol = set_field(mcontrol, MCONTROL_U, 1);
1107               mcontrol = set_field(mcontrol, MCONTROL_EXECUTE, bp.execute);
1108               mcontrol = set_field(mcontrol, MCONTROL_LOAD, bp.load);
1109               mcontrol = set_field(mcontrol, MCONTROL_STORE, bp.store);
1110               // For store triggers it's nicer to fire just before the
1111               // instruction than just after. However, gdb doesn't clear the
1112               // breakpoints and step before resuming from a store trigger.
1113               // That means that without extra code, you'll keep hitting the
1114               // same watchpoint over and over again. That's not useful at all.
1115               // Instead of fixing this the right way, just set timing=1 for
1116               // those triggers.
1117               if (bp.load || bp.store)
1118                 mcontrol = set_field(mcontrol, MCONTROL_TIMING, 1);
1119
1120               gs.dr_write(SLOT_DATA1, mcontrol);
1121               state = STATE_WRITE_ADDRESS;
1122             } else {
1123               bp.index++;
1124               write_new_index_program();
1125               state = STATE_CHECK_INDEX;
1126             }
1127           }
1128           break;
1129
1130         case STATE_WRITE_ADDRESS:
1131           {
1132             gs.dr_write_load(0, S0, SLOT_DATA1);
1133             gs.dr_write32(1, csrw(S0, CSR_TDATA2));
1134             gs.dr_write_jump(2);
1135             gs.dr_write(SLOT_DATA1, bp.vaddr);
1136             gs.set_interrupt(0);
1137             gs.send_packet("OK");
1138
1139             gs.hardware_breakpoints.insert(bp);
1140
1141             return true;
1142           }
1143       }
1144
1145       gs.set_interrupt(0);
1146       return false;
1147     }
1148
1149   private:
1150     enum {
1151       STATE_START,
1152       STATE_CHECK_INDEX,
1153       STATE_CHECK_MCONTROL,
1154       STATE_WRITE_ADDRESS
1155     } state;
1156     hardware_breakpoint_t bp;
1157 };
1158
1159 class maybe_save_tselect_op_t : public operation_t
1160 {
1161   public:
1162     maybe_save_tselect_op_t(gdbserver_t& gdbserver) : operation_t(gdbserver) {};
1163     bool perform_step(unsigned int step) {
1164       if (gs.tselect_valid)
1165         return true;
1166
1167       switch (step) {
1168         case 0:
1169           gs.dr_write32(0, csrr(S0, CSR_TDATA1));
1170           gs.dr_write_store(1, S0, SLOT_DATA0);
1171           gs.dr_write_jump(2);
1172           gs.set_interrupt(0);
1173           return false;
1174         case 1:
1175           gs.tselect = gs.dr_read(SLOT_DATA0);
1176           gs.tselect_valid = true;
1177           break;
1178       }
1179       return true;
1180     }
1181 };
1182
1183 class maybe_restore_tselect_op_t : public operation_t
1184 {
1185   public:
1186     maybe_restore_tselect_op_t(gdbserver_t& gdbserver) : operation_t(gdbserver) {};
1187     bool perform_step(unsigned int step) {
1188       if (gs.tselect_valid) {
1189         gs.dr_write_load(0, S0, SLOT_DATA1);
1190         gs.dr_write32(1, csrw(S0, CSR_TSELECT));
1191         gs.dr_write_jump(2);
1192         gs.dr_write(SLOT_DATA1, gs.tselect);
1193       }
1194       return true;
1195     }
1196 };
1197
1198 class hardware_breakpoint_remove_op_t : public operation_t
1199 {
1200   public:
1201     hardware_breakpoint_remove_op_t(gdbserver_t& gdbserver,
1202         hardware_breakpoint_t bp) :
1203       operation_t(gdbserver), bp(bp) {};
1204
1205     bool perform_step(unsigned int step) {
1206       gs.dr_write32(0, addi(S0, ZERO, bp.index));
1207       gs.dr_write32(1, csrw(S0, CSR_TSELECT));
1208       gs.dr_write32(2, csrw(ZERO, CSR_TDATA1));
1209       gs.dr_write_jump(3);
1210       gs.set_interrupt(0);
1211       return true;
1212     }
1213
1214   private:
1215     hardware_breakpoint_t bp;
1216 };
1217
1218 ////////////////////////////// gdbserver itself
1219
1220 gdbserver_t::gdbserver_t(uint16_t port, sim_t *sim) :
1221   xlen(0),
1222   sim(sim),
1223   client_fd(0),
1224   recv_buf(64 * 1024), send_buf(64 * 1024)
1225 {
1226   socket_fd = socket(AF_INET, SOCK_STREAM, 0);
1227   if (socket_fd == -1) {
1228     fprintf(stderr, "failed to make socket: %s (%d)\n", strerror(errno), errno);
1229     abort();
1230   }
1231
1232   fcntl(socket_fd, F_SETFL, O_NONBLOCK);
1233   int reuseaddr = 1;
1234   if (setsockopt(socket_fd, SOL_SOCKET, SO_REUSEADDR, &reuseaddr,
1235         sizeof(int)) == -1) {
1236     fprintf(stderr, "failed setsockopt: %s (%d)\n", strerror(errno), errno);
1237     abort();
1238   }
1239
1240   struct sockaddr_in addr;
1241   memset(&addr, 0, sizeof(addr));
1242   addr.sin_family = AF_INET;
1243   addr.sin_addr.s_addr = INADDR_ANY;
1244   addr.sin_port = htons(port);
1245
1246   if (bind(socket_fd, (struct sockaddr *) &addr, sizeof(addr)) == -1) {
1247     fprintf(stderr, "failed to bind socket: %s (%d)\n", strerror(errno), errno);
1248     abort();
1249   }
1250
1251   if (listen(socket_fd, 1) == -1) {
1252     fprintf(stderr, "failed to listen on socket: %s (%d)\n", strerror(errno), errno);
1253     abort();
1254   }
1255 }
1256
1257 unsigned int gdbserver_t::find_access_size(reg_t address, int length)
1258 {
1259   reg_t composite = address | length;
1260   if ((composite & 0x7) == 0 && xlen >= 64)
1261     return 8;
1262   if ((composite & 0x3) == 0)
1263     return 4;
1264   return 1;
1265 }
1266
1267 reg_t gdbserver_t::translate(reg_t vaddr)
1268 {
1269   unsigned int vm = virtual_memory();
1270   unsigned int levels, ptidxbits, ptesize;
1271
1272   switch (vm) {
1273     case VM_MBARE:
1274       return vaddr;
1275
1276     case VM_SV32:
1277       levels = 2;
1278       ptidxbits = 10;
1279       ptesize = 4;
1280       break;
1281     case VM_SV39:
1282       levels = 3;
1283       ptidxbits = 9;
1284       ptesize = 8;
1285       break;
1286     case VM_SV48:
1287       levels = 4;
1288       ptidxbits = 9;
1289       ptesize = 8;
1290       break;
1291
1292     default:
1293       {
1294         char buf[100];
1295         sprintf(buf, "VM mode %d is not supported by gdbserver.cc.", vm);
1296         die(buf);
1297         return true;        // die doesn't return, but gcc doesn't know that.
1298       }
1299   }
1300
1301   // Handle page tables here. There's a bunch of duplicated code with
1302   // collect_translation_info_op_t. :-(
1303   reg_t base = sptbr << PGSHIFT;
1304   int ptshift = (levels - 1) * ptidxbits;
1305   for (unsigned int i = 0; i < levels; i++, ptshift -= ptidxbits) {
1306     reg_t idx = (vaddr >> (PGSHIFT + ptshift)) & ((1 << ptidxbits) - 1);
1307
1308     reg_t pte_addr = base + idx * ptesize;
1309     auto it = pte_cache.find(pte_addr);
1310     if (it == pte_cache.end()) {
1311       fprintf(stderr, "ERROR: gdbserver tried to translate 0x%016" PRIx64
1312           " without first collecting the relevant PTEs.\n", vaddr);
1313       die("gdbserver_t::translate()");
1314     }
1315
1316     reg_t pte = pte_cache[pte_addr];
1317     reg_t ppn = pte >> PTE_PPN_SHIFT;
1318
1319     if (PTE_TABLE(pte)) { // next level of page table
1320       base = ppn << PGSHIFT;
1321     } else {
1322       // We've collected all the data required for the translation.
1323       reg_t vpn = vaddr >> PGSHIFT;
1324       reg_t paddr = (ppn | (vpn & ((reg_t(1) << ptshift) - 1))) << PGSHIFT;
1325       paddr += vaddr & (PGSIZE-1);
1326       D(fprintf(stderr, "gdbserver translate 0x%lx -> 0x%lx\n", vaddr, paddr));
1327       return paddr;
1328     }
1329   }
1330
1331   fprintf(stderr, "ERROR: gdbserver tried to translate 0x%016" PRIx64
1332           " but the relevant PTEs are invalid.\n", vaddr);
1333   // TODO: Is it better to throw an exception here?
1334   return -1;
1335 }
1336
1337 unsigned int gdbserver_t::privilege_mode()
1338 {
1339   unsigned int mode = get_field(dcsr, DCSR_PRV);
1340   if (get_field(mstatus, MSTATUS_MPRV))
1341     mode = get_field(mstatus, MSTATUS_MPP);
1342   return mode;
1343 }
1344
1345 unsigned int gdbserver_t::virtual_memory()
1346 {
1347   unsigned int mode = privilege_mode();
1348   if (mode == PRV_M)
1349     return VM_MBARE;
1350   return get_field(mstatus, MSTATUS_VM);
1351 }
1352
1353 void gdbserver_t::dr_write32(unsigned int index, uint32_t value)
1354 {
1355   sim->debug_module.ram_write32(index, value);
1356 }
1357
1358 void gdbserver_t::dr_write64(unsigned int index, uint64_t value)
1359 {
1360   dr_write32(index, value);
1361   dr_write32(index+1, value >> 32);
1362 }
1363
1364 void gdbserver_t::dr_write(enum slot slot, uint64_t value)
1365 {
1366   switch (xlen) {
1367     case 32:
1368       dr_write32(slot_offset32[slot], value);
1369       break;
1370     case 64:
1371       dr_write64(slot_offset64[slot], value);
1372       break;
1373     case 128:
1374     default:
1375       abort();
1376   }
1377 }
1378
1379 void gdbserver_t::dr_write_jump(unsigned int index)
1380 {
1381   dr_write32(index, jal(0,
1382         (uint32_t) (DEBUG_ROM_RESUME - (DEBUG_RAM_START + 4*index))));
1383 }
1384
1385 void gdbserver_t::dr_write_store(unsigned int index, unsigned int reg, enum slot slot)
1386 {
1387   assert(slot != SLOT_INST0 || index > 2);
1388   assert(slot != SLOT_DATA0 || index < 4 || index > 6);
1389   assert(slot != SLOT_DATA1 || index < 5 || index > 10);
1390   assert(slot != SLOT_DATA_LAST || index < 6 || index > 14);
1391   switch (xlen) {
1392     case 32:
1393       return dr_write32(index,
1394           sw(reg, 0, (uint16_t) DEBUG_RAM_START + 4 * slot_offset32[slot]));
1395     case 64:
1396       return dr_write32(index,
1397           sd(reg, 0, (uint16_t) DEBUG_RAM_START + 4 * slot_offset64[slot]));
1398     case 128:
1399       return dr_write32(index,
1400           sq(reg, 0, (uint16_t) DEBUG_RAM_START + 4 * slot_offset128[slot]));
1401     default:
1402       fprintf(stderr, "xlen is %d!\n", xlen);
1403       abort();
1404   }
1405 }
1406
1407 void gdbserver_t::dr_write_load(unsigned int index, unsigned int reg, enum slot slot)
1408 {
1409   switch (xlen) {
1410     case 32:
1411       return dr_write32(index,
1412           lw(reg, 0, (uint16_t) DEBUG_RAM_START + 4 * slot_offset32[slot]));
1413     case 64:
1414       return dr_write32(index,
1415           ld(reg, 0, (uint16_t) DEBUG_RAM_START + 4 * slot_offset64[slot]));
1416     case 128:
1417       return dr_write32(index,
1418           lq(reg, 0, (uint16_t) DEBUG_RAM_START + 4 * slot_offset128[slot]));
1419     default:
1420       fprintf(stderr, "xlen is %d!\n", xlen);
1421       abort();
1422   }
1423 }
1424
1425 uint32_t gdbserver_t::dr_read32(unsigned int index)
1426 {
1427   uint32_t value = sim->debug_module.ram_read32(index);
1428   D(fprintf(stderr, "read32(%d) -> 0x%x\n", index, value));
1429   return value;
1430 }
1431
1432 uint64_t gdbserver_t::dr_read64(unsigned int index)
1433 {
1434   return ((uint64_t) dr_read32(index+1) << 32) | dr_read32(index);
1435 }
1436
1437 uint64_t gdbserver_t::dr_read(enum slot slot)
1438 {
1439   switch (xlen) {
1440     case 32:
1441       return dr_read32(slot_offset32[slot]);
1442     case 64:
1443       return dr_read64(slot_offset64[slot]);
1444     case 128:
1445       abort();
1446     default:
1447       abort();
1448   }
1449 }
1450
1451 void gdbserver_t::add_operation(operation_t* operation)
1452 {
1453   operation_queue.push(operation);
1454 }
1455
1456 void gdbserver_t::accept()
1457 {
1458   client_fd = ::accept(socket_fd, NULL, NULL);
1459   if (client_fd == -1) {
1460     if (errno == EAGAIN) {
1461       // No client waiting to connect right now.
1462     } else {
1463       fprintf(stderr, "failed to accept on socket: %s (%d)\n", strerror(errno),
1464           errno);
1465       abort();
1466     }
1467   } else {
1468     fcntl(client_fd, F_SETFL, O_NONBLOCK);
1469
1470     expect_ack = false;
1471     extended_mode = false;
1472
1473     // gdb wants the core to be halted when it attaches.
1474     add_operation(new halt_op_t(*this));
1475   }
1476 }
1477
1478 void gdbserver_t::read()
1479 {
1480   // Reading from a non-blocking socket still blocks if there is no data
1481   // available.
1482
1483   size_t count = recv_buf.contiguous_empty_size();
1484   assert(count > 0);
1485   ssize_t bytes = ::read(client_fd, recv_buf.contiguous_empty(), count);
1486   if (bytes == -1) {
1487     if (errno == EAGAIN) {
1488       // We'll try again the next call.
1489     } else {
1490       fprintf(stderr, "failed to read on socket: %s (%d)\n", strerror(errno), errno);
1491       abort();
1492     }
1493   } else if (bytes == 0) {
1494     // The remote disconnected.
1495     client_fd = 0;
1496     processor_t *p = sim->get_core(0);
1497     // TODO p->set_halted(false, HR_NONE);
1498     recv_buf.reset();
1499     send_buf.reset();
1500   } else {
1501     recv_buf.data_added(bytes);
1502   }
1503 }
1504
1505 void gdbserver_t::write()
1506 {
1507   if (send_buf.empty())
1508     return;
1509
1510   while (!send_buf.empty()) {
1511     unsigned int count = send_buf.contiguous_data_size();
1512     assert(count > 0);
1513     ssize_t bytes = ::write(client_fd, send_buf.contiguous_data(), count);
1514     if (bytes == -1) {
1515       fprintf(stderr, "failed to write to socket: %s (%d)\n", strerror(errno), errno);
1516       abort();
1517     } else if (bytes == 0) {
1518       // Client can't take any more data right now.
1519       break;
1520     } else {
1521       D(fprintf(stderr, "wrote %ld bytes: ", bytes));
1522       for (unsigned int i = 0; i < bytes; i++) {
1523         D(fprintf(stderr, "%c", send_buf[i]));
1524       }
1525       D(fprintf(stderr, "\n"));
1526       send_buf.consume(bytes);
1527     }
1528   }
1529 }
1530
1531 void print_packet(const std::vector<uint8_t> &packet)
1532 {
1533   for (uint8_t c : packet) {
1534     if (c >= ' ' and c <= '~')
1535       fprintf(stderr, "%c", c);
1536     else
1537       fprintf(stderr, "\\x%02x", c);
1538   }
1539   fprintf(stderr, "\n");
1540 }
1541
1542 uint8_t compute_checksum(const std::vector<uint8_t> &packet)
1543 {
1544   uint8_t checksum = 0;
1545   for (auto i = packet.begin() + 1; i != packet.end() - 3; i++ ) {
1546     checksum += *i;
1547   }
1548   return checksum;
1549 }
1550
1551 uint8_t character_hex_value(uint8_t character)
1552 {
1553   if (character >= '0' && character <= '9')
1554     return character - '0';
1555   if (character >= 'a' && character <= 'f')
1556     return 10 + character - 'a';
1557   if (character >= 'A' && character <= 'F')
1558     return 10 + character - 'A';
1559   return 0xff;
1560 }
1561
1562 uint8_t extract_checksum(const std::vector<uint8_t> &packet)
1563 {
1564   return character_hex_value(*(packet.end() - 1)) +
1565     16 * character_hex_value(*(packet.end() - 2));
1566 }
1567
1568 void gdbserver_t::process_requests()
1569 {
1570   // See https://sourceware.org/gdb/onlinedocs/gdb/Remote-Protocol.html
1571
1572   while (!recv_buf.empty()) {
1573     std::vector<uint8_t> packet;
1574     for (unsigned int i = 0; i < recv_buf.size(); i++) {
1575       uint8_t b = recv_buf[i];
1576
1577       if (packet.empty() && expect_ack && b == '+') {
1578         recv_buf.consume(1);
1579         break;
1580       }
1581
1582       if (packet.empty() && b == 3) {
1583         D(fprintf(stderr, "Received interrupt\n"));
1584         recv_buf.consume(1);
1585         handle_interrupt();
1586         break;
1587       }
1588
1589       if (b == '$') {
1590         // Start of new packet.
1591         if (!packet.empty()) {
1592           fprintf(stderr, "Received malformed %ld-byte packet from debug client: ",
1593               packet.size());
1594           print_packet(packet);
1595           recv_buf.consume(i);
1596           break;
1597         }
1598       }
1599
1600       packet.push_back(b);
1601
1602       // Packets consist of $<packet-data>#<checksum>
1603       // where <checksum> is
1604       if (packet.size() >= 4 &&
1605           packet[packet.size()-3] == '#') {
1606         handle_packet(packet);
1607         recv_buf.consume(i+1);
1608         break;
1609       }
1610     }
1611     // There's a partial packet in the buffer. Wait until we get more data to
1612     // process it.
1613     if (packet.size()) {
1614       break;
1615     }
1616   }
1617 }
1618
1619 void gdbserver_t::handle_halt_reason(const std::vector<uint8_t> &packet)
1620 {
1621   send_packet("S00");
1622 }
1623
1624 void gdbserver_t::handle_general_registers_read(const std::vector<uint8_t> &packet)
1625 {
1626   add_operation(new general_registers_read_op_t(*this));
1627 }
1628
1629 void gdbserver_t::set_interrupt(uint32_t hartid) {
1630   sim->debug_module.set_interrupt(hartid);
1631 }
1632
1633 // First byte is the most-significant one.
1634 // Eg. "08675309" becomes 0x08675309.
1635 uint64_t consume_hex_number(std::vector<uint8_t>::const_iterator &iter,
1636     std::vector<uint8_t>::const_iterator end)
1637 {
1638   uint64_t value = 0;
1639
1640   while (iter != end) {
1641     uint8_t c = *iter;
1642     uint64_t c_value = character_hex_value(c);
1643     if (c_value > 15)
1644       break;
1645     iter++;
1646     value <<= 4;
1647     value += c_value;
1648   }
1649   return value;
1650 }
1651
1652 // First byte is the least-significant one.
1653 // Eg. "08675309" becomes 0x09536708
1654 uint64_t consume_hex_number_le(std::vector<uint8_t>::const_iterator &iter,
1655     std::vector<uint8_t>::const_iterator end)
1656 {
1657   uint64_t value = 0;
1658   unsigned int shift = 4;
1659
1660   while (iter != end) {
1661     uint8_t c = *iter;
1662     uint64_t c_value = character_hex_value(c);
1663     if (c_value > 15)
1664       break;
1665     iter++;
1666     value |= c_value << shift;
1667     if ((shift % 8) == 0)
1668       shift += 12;
1669     else
1670       shift -= 4;
1671   }
1672   return value;
1673 }
1674
1675 void consume_string(std::string &str, std::vector<uint8_t>::const_iterator &iter,
1676     std::vector<uint8_t>::const_iterator end, uint8_t separator)
1677 {
1678   while (iter != end && *iter != separator) {
1679     str.append(1, (char) *iter);
1680     iter++;
1681   }
1682 }
1683
1684 void gdbserver_t::handle_register_read(const std::vector<uint8_t> &packet)
1685 {
1686   // p n
1687
1688   std::vector<uint8_t>::const_iterator iter = packet.begin() + 2;
1689   unsigned int n = consume_hex_number(iter, packet.end());
1690   if (*iter != '#')
1691     return send_packet("E01");
1692
1693   add_operation(new register_read_op_t(*this, n));
1694 }
1695
1696 void gdbserver_t::handle_register_write(const std::vector<uint8_t> &packet)
1697 {
1698   // P n...=r...
1699
1700   std::vector<uint8_t>::const_iterator iter = packet.begin() + 2;
1701   unsigned int n = consume_hex_number(iter, packet.end());
1702   if (*iter != '=')
1703     return send_packet("E05");
1704   iter++;
1705
1706   reg_t value = consume_hex_number_le(iter, packet.end());
1707   if (*iter != '#')
1708     return send_packet("E06");
1709
1710   processor_t *p = sim->get_core(0);
1711
1712   add_operation(new register_write_op_t(*this, n, value));
1713
1714   return send_packet("OK");
1715 }
1716
1717 void gdbserver_t::handle_memory_read(const std::vector<uint8_t> &packet)
1718 {
1719   // m addr,length
1720   std::vector<uint8_t>::const_iterator iter = packet.begin() + 2;
1721   reg_t address = consume_hex_number(iter, packet.end());
1722   if (*iter != ',')
1723     return send_packet("E10");
1724   iter++;
1725   reg_t length = consume_hex_number(iter, packet.end());
1726   if (*iter != '#')
1727     return send_packet("E11");
1728
1729   add_operation(new collect_translation_info_op_t(*this, address, length));
1730   add_operation(new memory_read_op_t(*this, address, length));
1731 }
1732
1733 void gdbserver_t::handle_memory_binary_write(const std::vector<uint8_t> &packet)
1734 {
1735   // X addr,length:XX...
1736   std::vector<uint8_t>::const_iterator iter = packet.begin() + 2;
1737   reg_t address = consume_hex_number(iter, packet.end());
1738   if (*iter != ',')
1739     return send_packet("E20");
1740   iter++;
1741   reg_t length = consume_hex_number(iter, packet.end());
1742   if (*iter != ':')
1743     return send_packet("E21");
1744   iter++;
1745
1746   if (length == 0) {
1747     return send_packet("OK");
1748   }
1749
1750   unsigned char *data = new unsigned char[length];
1751   for (unsigned int i = 0; i < length; i++) {
1752     if (iter == packet.end()) {
1753       return send_packet("E22");
1754     }
1755     uint8_t c = *iter;
1756     iter++;
1757     if (c == '}') {
1758       // The binary data representation uses 7d (ascii ‘}’) as an escape
1759       // character. Any escaped byte is transmitted as the escape character
1760       // followed by the original character XORed with 0x20. For example, the
1761       // byte 0x7d would be transmitted as the two bytes 0x7d 0x5d. The bytes
1762       // 0x23 (ascii ‘#’), 0x24 (ascii ‘$’), and 0x7d (ascii ‘}’) must always
1763       // be escaped.
1764       if (iter == packet.end()) {
1765         return send_packet("E23");
1766       }
1767       c = (*iter) ^ 0x20;
1768       iter++;
1769     }
1770     data[i] = c;
1771   }
1772   if (*iter != '#')
1773     return send_packet("E4b"); // EOVERFLOW
1774
1775   add_operation(new collect_translation_info_op_t(*this, address, length));
1776   add_operation(new memory_write_op_t(*this, address, length, data));
1777 }
1778
1779 void gdbserver_t::handle_continue(const std::vector<uint8_t> &packet)
1780 {
1781   // c [addr]
1782   processor_t *p = sim->get_core(0);
1783   if (packet[2] != '#') {
1784     std::vector<uint8_t>::const_iterator iter = packet.begin() + 2;
1785     dpc = consume_hex_number(iter, packet.end());
1786     if (*iter != '#')
1787       return send_packet("E30");
1788   }
1789
1790   add_operation(new maybe_restore_tselect_op_t(*this));
1791   add_operation(new continue_op_t(*this, false));
1792 }
1793
1794 void gdbserver_t::handle_step(const std::vector<uint8_t> &packet)
1795 {
1796   // s [addr]
1797   if (packet[2] != '#') {
1798     std::vector<uint8_t>::const_iterator iter = packet.begin() + 2;
1799     die("handle_step");
1800     //p->state.pc = consume_hex_number(iter, packet.end());
1801     if (*iter != '#')
1802       return send_packet("E40");
1803   }
1804
1805   add_operation(new maybe_restore_tselect_op_t(*this));
1806   add_operation(new continue_op_t(*this, true));
1807 }
1808
1809 void gdbserver_t::handle_kill(const std::vector<uint8_t> &packet)
1810 {
1811   // k
1812   // The exact effect of this packet is not specified.
1813   // Looks like OpenOCD disconnects?
1814   // TODO
1815 }
1816
1817 void gdbserver_t::handle_extended(const std::vector<uint8_t> &packet)
1818 {
1819   // Enable extended mode. In extended mode, the remote server is made
1820   // persistent. The ‘R’ packet is used to restart the program being debugged.
1821   send_packet("OK");
1822   extended_mode = true;
1823 }
1824
1825 void gdbserver_t::software_breakpoint_insert(reg_t vaddr, unsigned int size)
1826 {
1827   fence_i_required = true;
1828   add_operation(new collect_translation_info_op_t(*this, vaddr, size));
1829   unsigned char* inst = new unsigned char[4];
1830   if (size == 2) {
1831     inst[0] = C_EBREAK & 0xff;
1832     inst[1] = (C_EBREAK >> 8) & 0xff;
1833   } else {
1834     inst[0] = EBREAK & 0xff;
1835     inst[1] = (EBREAK >> 8) & 0xff;
1836     inst[2] = (EBREAK >> 16) & 0xff;
1837     inst[3] = (EBREAK >> 24) & 0xff;
1838   }
1839
1840   software_breakpoint_t bp = {
1841     .vaddr = vaddr,
1842     .size = size
1843   };
1844   software_breakpoints[vaddr] = bp;
1845   add_operation(new memory_read_op_t(*this, bp.vaddr, bp.size,
1846         software_breakpoints[bp.vaddr].instruction));
1847   add_operation(new memory_write_op_t(*this, bp.vaddr, bp.size, inst));
1848 }
1849
1850 void gdbserver_t::software_breakpoint_remove(reg_t vaddr, unsigned int size)
1851 {
1852   fence_i_required = true;
1853   add_operation(new collect_translation_info_op_t(*this, vaddr, size));
1854
1855   software_breakpoint_t found_bp = software_breakpoints[vaddr];
1856   unsigned char* instruction = new unsigned char[4];
1857   memcpy(instruction, found_bp.instruction, 4);
1858   add_operation(new memory_write_op_t(*this, found_bp.vaddr,
1859         found_bp.size, instruction));
1860   software_breakpoints.erase(vaddr);
1861 }
1862
1863 void gdbserver_t::hardware_breakpoint_insert(const hardware_breakpoint_t &bp)
1864 {
1865   add_operation(new maybe_save_tselect_op_t(*this));
1866   add_operation(new hardware_breakpoint_insert_op_t(*this, bp));
1867 }
1868
1869 void gdbserver_t::hardware_breakpoint_remove(const hardware_breakpoint_t &bp)
1870 {
1871   add_operation(new maybe_save_tselect_op_t(*this));
1872   hardware_breakpoint_t found = *hardware_breakpoints.find(bp);
1873   add_operation(new hardware_breakpoint_remove_op_t(*this, found));
1874 }
1875
1876 void gdbserver_t::handle_breakpoint(const std::vector<uint8_t> &packet)
1877 {
1878   // insert: Z type,addr,length
1879   // remove: z type,addr,length
1880
1881   // type: 0 - software breakpoint, 1 - hardware breakpoint, 2 - write
1882   // watchpoint, 3 - read watchpoint, 4 - access watchpoint; addr is address;
1883   // length is in bytes. For a software breakpoint, length specifies the size
1884   // of the instruction to be patched. For hardware breakpoints and watchpoints
1885   // length specifies the memory region to be monitored. To avoid potential
1886   // problems with duplicate packets, the operations should be implemented in
1887   // an idempotent way.
1888
1889   bool insert = (packet[1] == 'Z');
1890   std::vector<uint8_t>::const_iterator iter = packet.begin() + 2;
1891   gdb_breakpoint_type_t type = static_cast<gdb_breakpoint_type_t>(
1892       consume_hex_number(iter, packet.end()));
1893   if (*iter != ',')
1894     return send_packet("E50");
1895   iter++;
1896   reg_t address = consume_hex_number(iter, packet.end());
1897   if (*iter != ',')
1898     return send_packet("E51");
1899   iter++;
1900   unsigned int size = consume_hex_number(iter, packet.end());
1901   // There may be more options after a ; here, but we don't support that.
1902   if (*iter != '#')
1903     return send_packet("E52");
1904
1905   switch (type) {
1906     case GB_SOFTWARE:
1907       if (size != 2 && size != 4) {
1908         return send_packet("E53");
1909       }
1910       if (insert) {
1911         software_breakpoint_insert(address, size);
1912       } else {
1913         software_breakpoint_remove(address, size);
1914       }
1915       break;
1916
1917     case GB_HARDWARE:
1918     case GB_WRITE:
1919     case GB_READ:
1920     case GB_ACCESS:
1921       {
1922         hardware_breakpoint_t bp = {
1923           .vaddr = address,
1924           .size = size
1925         };
1926         bp.load = (type == GB_READ || type == GB_ACCESS);
1927         bp.store = (type == GB_WRITE || type == GB_ACCESS);
1928         bp.execute = (type == GB_HARDWARE || type == GB_ACCESS);
1929         if (insert) {
1930           hardware_breakpoint_insert(bp);
1931           // Insert might fail if there's no space, so the insert operation will
1932           // send its own OK (or not).
1933           return;
1934         } else {
1935           hardware_breakpoint_remove(bp);
1936         }
1937       }
1938       break;
1939
1940     default:
1941       return send_packet("E56");
1942   }
1943
1944   return send_packet("OK");
1945 }
1946
1947 void gdbserver_t::handle_query(const std::vector<uint8_t> &packet)
1948 {
1949   std::string name;
1950   std::vector<uint8_t>::const_iterator iter = packet.begin() + 2;
1951
1952   consume_string(name, iter, packet.end(), ':');
1953   if (iter != packet.end())
1954     iter++;
1955   if (name == "Supported") {
1956     start_packet();
1957     while (iter != packet.end()) {
1958       std::string feature;
1959       consume_string(feature, iter, packet.end(), ';');
1960       if (iter != packet.end())
1961         iter++;
1962       if (feature == "swbreak+") {
1963         send("swbreak+;");
1964       }
1965     }
1966     send("PacketSize=131072;");
1967     return end_packet();
1968   }
1969
1970   D(fprintf(stderr, "Unsupported query %s\n", name.c_str()));
1971   return send_packet("");
1972 }
1973
1974 void gdbserver_t::handle_packet(const std::vector<uint8_t> &packet)
1975 {
1976   if (compute_checksum(packet) != extract_checksum(packet)) {
1977     fprintf(stderr, "Received %ld-byte packet with invalid checksum\n", packet.size());
1978     fprintf(stderr, "Computed checksum: %x\n", compute_checksum(packet));
1979     print_packet(packet);
1980     send("-");
1981     return;
1982   }
1983
1984   D(fprintf(stderr, "Received %ld-byte packet from debug client: ", packet.size()));
1985   D(print_packet(packet));
1986   send("+");
1987
1988   switch (packet[1]) {
1989     case '!':
1990       return handle_extended(packet);
1991     case '?':
1992       return handle_halt_reason(packet);
1993     case 'g':
1994       return handle_general_registers_read(packet);
1995 //    case 'k':
1996 //      return handle_kill(packet);
1997     case 'm':
1998       return handle_memory_read(packet);
1999 //    case 'M':
2000 //      return handle_memory_write(packet);
2001     case 'X':
2002       return handle_memory_binary_write(packet);
2003     case 'p':
2004       return handle_register_read(packet);
2005     case 'P':
2006       return handle_register_write(packet);
2007     case 'c':
2008       return handle_continue(packet);
2009     case 's':
2010       return handle_step(packet);
2011     case 'z':
2012     case 'Z':
2013       return handle_breakpoint(packet);
2014     case 'q':
2015     case 'Q':
2016       return handle_query(packet);
2017   }
2018
2019   // Not supported.
2020   D(fprintf(stderr, "** Unsupported packet: "));
2021   D(print_packet(packet));
2022   send_packet("");
2023 }
2024
2025 void gdbserver_t::handle_interrupt()
2026 {
2027   processor_t *p = sim->get_core(0);
2028   add_operation(new halt_op_t(*this, true));
2029 }
2030
2031 void gdbserver_t::handle()
2032 {
2033   if (client_fd > 0) {
2034     processor_t *p = sim->get_core(0);
2035
2036     bool interrupt = sim->debug_module.get_interrupt(0);
2037
2038     if (!interrupt && !operation_queue.empty()) {
2039       operation_t *operation = operation_queue.front();
2040       if (operation->step()) {
2041         operation_queue.pop();
2042         delete operation;
2043       }
2044     }
2045
2046     bool halt_notification = sim->debug_module.get_halt_notification(0);
2047     if (halt_notification) {
2048       sim->debug_module.clear_halt_notification(0);
2049       add_operation(new halt_op_t(*this, true));
2050     }
2051
2052     this->read();
2053     this->write();
2054
2055   } else {
2056     this->accept();
2057   }
2058
2059   if (operation_queue.empty()) {
2060     this->process_requests();
2061   }
2062 }
2063
2064 void gdbserver_t::send(const char* msg)
2065 {
2066   unsigned int length = strlen(msg);
2067   for (const char *c = msg; *c; c++)
2068     running_checksum += *c;
2069   send_buf.append((const uint8_t *) msg, length);
2070 }
2071
2072 void gdbserver_t::send(uint64_t value)
2073 {
2074   char buffer[3];
2075   for (unsigned int i = 0; i < 8; i++) {
2076     sprintf(buffer, "%02x", (int) (value & 0xff));
2077     send(buffer);
2078     value >>= 8;
2079   }
2080 }
2081
2082 void gdbserver_t::send(uint32_t value)
2083 {
2084   char buffer[3];
2085   for (unsigned int i = 0; i < 4; i++) {
2086     sprintf(buffer, "%02x", (int) (value & 0xff));
2087     send(buffer);
2088     value >>= 8;
2089   }
2090 }
2091
2092 void gdbserver_t::send(uint8_t value)
2093 {
2094   char buffer[3];
2095   sprintf(buffer, "%02x", (int) value);
2096   send(buffer);
2097 }
2098
2099 void gdbserver_t::send_packet(const char* data)
2100 {
2101   start_packet();
2102   send(data);
2103   end_packet();
2104   expect_ack = true;
2105 }
2106
2107 void gdbserver_t::start_packet()
2108 {
2109   send("$");
2110   running_checksum = 0;
2111 }
2112
2113 void gdbserver_t::end_packet(const char* data)
2114 {
2115   if (data) {
2116     send(data);
2117   }
2118
2119   char checksum_string[4];
2120   sprintf(checksum_string, "#%02x", running_checksum);
2121   send(checksum_string);
2122   expect_ack = true;
2123 }