c86e5373489f4be4f7e1701716da74f01d214fce
[riscv-isa-sim.git] / riscv / insns / amo_and.h
1 require64;
2 reg_t v = mmu.load_uint64(RB);
3 mmu.store_uint64(RB, RA & v);
4 RC = v;