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c178f9af1cc8e8f61bd4a638efbb2118dc9d7227
[riscv-isa-sim.git]
/
riscv
/
insns
/
amoor_w.h
1
reg_t v
=
MMU
.
load_int32
(
RS1
);
2
MMU
.
store_uint32
(
RS1
,
RS2
|
v
);
3
WRITE_RD
(
v
);