9889b646e3e194540724579e1b3946514e55d115
[riscv-isa-sim.git] / riscv / insns / amoxor_w.h
1 require_extension('A');
2 reg_t v = MMU.load_int32(RS1);
3 MMU.store_uint32(RS1, RS2 ^ v);
4 WRITE_RD(v);