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f59a43e59f71d1ab8302b38224074134fe1e77c4
[riscv-isa-sim.git]
/
riscv
/
insns
/
amoxor_w.h
1
reg_t v
=
MMU
.
load_int32
(
RS1
);
2
MMU
.
store_uint32
(
RS1
,
RS2
^
v
);
3
RD
=
v
;