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0be27a94a4cc1d16cba37f9ac34cd38ddf258437
[riscv-isa-sim.git]
/
riscv
/
insns
/
c_flw.h
1
require_extension
(
'C'
);
2
if
(
xlen
==
32
) {
3
require_extension
(
'F'
);
4
require_fp
;
5
WRITE_RVC_FRS2S
(
MMU
.
load_int32
(
RVC_RS1S
+
insn
.
rvc_lw_imm
()));
6
}
else
{
// c.ld
7
WRITE_RVC_RS2S
(
MMU
.
load_int64
(
RVC_RS1S
+
insn
.
rvc_ld_imm
()));
8
}