87a59010a78d259a163ef0d5a509bdb9b5de12f2
[riscv-isa-sim.git] / riscv / insns / c_slliw.h
1 require_extension('C');
2 require_rv64;
3 require(insn.rvc_rd() != 0);
4 require(insn.rvc_imm() < 32);
5 WRITE_RD(sext32(RVC_RS1 << insn.rvc_imm()));