fd878a2f3e8a50bef036289924d0f5ddc7ceea7f
[riscv-isa-sim.git] / riscv / insns / divu.h
1 reg_t lhs = zext_xprlen(RS1);
2 reg_t rhs = zext_xprlen(RS2);
3 if(rhs == 0)
4 WRITE_RD(UINT64_MAX);
5 else
6 WRITE_RD(sext_xprlen(lhs / rhs));