296bb9e16f52d11fa5d13a4332792d2724ae851b
[riscv-isa-sim.git] / riscv / insns / divuw.h
1 if(uint32_t(RS2) == 0)
2 RD = sext32(UINT32_MAX);
3 else
4 RD = sext32(uint32_t(RS1)/uint32_t(RS2));