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b905d31f2a7b70f42f3deb86cfbdb32df03981a8
[riscv-isa-sim.git]
/
riscv
/
insns
/
dmfc0.h
1
require_supervisor
;
2
require64
;
3
4
switch
(
insn
.
rtype
.
rs
)
5
{
6
case
0
:
7
RT
=
sr
;
8
break
;
9
case
1
:
10
RT
=
epc
;
11
break
;
12
case
2
:
13
RT
=
badvaddr
;
14
break
;
15
case
3
:
16
RT
=
ebase
;
17
break
;
18
19
case
8
:
20
RT
=
MEMSIZE
>>
12
;
21
break
;
22
23
case
17
:
24
RT
=
sim
->
get_fromhost
();
25
break
;
26
27
default
:
28
RT
= -
1
;
29
}