bef9ef2e26769c82fd37862cb3023de7e50f1d4b
[riscv-isa-sim.git] / riscv / insns / dret.h
1 require_privilege(PRV_M);
2 set_pc_and_serialize(STATE.dpc);
3 /* The debug spec says we can't crash when prv is set to an invalid value. */
4 if (p->validate_priv(STATE.dcsr.prv)) {
5 p->set_privilege(STATE.dcsr.prv);
6 }
7
8 /* We're not in Debug Mode anymore. */
9 STATE.dcsr.cause = 0;
10
11 if (STATE.dcsr.step)
12 STATE.single_step = STATE.STEP_STEPPING;