e298ac722bca931646fe052a85448590aae09e78
[riscv-isa-sim.git] / riscv / insns / ecall.h
1 switch (STATE.prv)
2 {
3 case PRV_U: throw trap_user_ecall();
4 case PRV_S: throw trap_supervisor_ecall();
5 case PRV_M: throw trap_machine_ecall();
6 default: abort();
7 }