3e5963dc99b86c4f5ec1eb90a9a1803a434b908c
[riscv-isa-sim.git] / riscv / insns / fadd_d.h
1 require_extension('D');
2 require_fp;
3 softfloat_roundingMode = RM;
4 WRITE_FRD(f64_mulAdd(FRS1, 0x3ff0000000000000ULL, FRS2));
5 set_fp_exceptions;