ee323f34be8bb46b1a7da944faea112947bfad9a
[riscv-isa-sim.git] / riscv / insns / fcvt_l_d.h
1 require_extension('D');
2 require_rv64;
3 require_fp;
4 softfloat_roundingMode = RM;
5 WRITE_RD(f64_to_i64(FRS1, RM, true));
6 set_fp_exceptions;