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f14cc19a37798d4e2032cf69bc2b233b02c50c8c
[riscv-isa-sim.git]
/
riscv
/
insns
/
fcvt_w_s.h
1
require_fp
;
2
softfloat_roundingMode
=
RM
;
3
RD
=
sext32
(
f32_to_i32
(
FRS1
,
RM
,
true
));
4
set_fp_exceptions
;