bf90356b6748c68b22dfb1f5eb4f2b2e3a64f464
[riscv-isa-sim.git] / riscv / insns / fmax_s.h
1 require_extension('F');
2 require_fp;
3 WRITE_FRD(f32_le_quiet(f32(FRS2), f32(FRS1)) || isNaNF32UI(FRS2) ? FRS1 : FRS2);
4 if ((isNaNF32UI(FRS1) && isNaNF32UI(FRS2)) || softfloat_exceptionFlags)
5 WRITE_FRD(defaultNaNF32UI);
6 set_fp_exceptions;