cc673a0cab87f8ad12ff6d0cd05c150475809370
[riscv-isa-sim.git] / riscv / insns / fmin_s.h
1 require_extension('F');
2 require_fp;
3 WRITE_FRD(isNaNF32UI(FRS2) || f32_lt_quiet(FRS1,FRS2) /* && FRS1 not NaN */
4 ? FRS1 : FRS2);
5 set_fp_exceptions;