696f8226ec90fa77de89c67b8f46586681f6eee9
[riscv-isa-sim.git] / riscv / insns / fmsub_d.h
1 require_extension('D');
2 require_fp;
3 softfloat_roundingMode = RM;
4 WRITE_FRD(f64_mulAdd(FRS1, FRS2, FRS3 ^ (uint64_t)INT64_MIN));
5 set_fp_exceptions;