45945dac4a48fd1230ddc5174e94a9915c896a24
[riscv-isa-sim.git] / riscv / insns / fmsub_s.h
1 require_extension('F');
2 require_fp;
3 softfloat_roundingMode = RM;
4 WRITE_FRD(f32_mulAdd(f32(FRS1), f32(FRS2), f32(FRS3 ^ (uint32_t)INT32_MIN)).v);
5 set_fp_exceptions;