3be27d09b5f01d952855d024a9cf1ca4ae4e06d6
[riscv-isa-sim.git] / riscv / insns / fnmsub_s.h
1 require_extension('F');
2 require_fp;
3 softfloat_roundingMode = RM;
4 WRITE_FRD(f32_mulAdd(FRS1 ^ (uint32_t)INT32_MIN, FRS2, FRS3));
5 set_fp_exceptions;