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6a0f853f4739f07d337afb07d39afa21de65bc84
[riscv-isa-sim.git]
/
riscv
/
insns
/
fsub_s.h
1
require_extension
(
'F'
);
2
require_fp
;
3
softfloat_roundingMode
=
RM
;
4
WRITE_FRD
(
f32_mulAdd
(
FRS1
,
0x3f800000
,
FRS2
^ (
uint32_t
)
INT32_MIN
));
5
set_fp_exceptions
;