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767251f9e07775dfe2edc01b726f1f661e43feb5
[riscv-isa-sim.git]
/
riscv
/
insns
/
lr_w.h
1
require_extension
(
'A'
);
2
p
->
get_state
()->
load_reservation
=
RS1
;
3
WRITE_RD
(
MMU
.
load_int32
(
RS1
));