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5535baf15b9a41ad0d5c1733191a8ca11b6e66bd
[riscv-isa-sim.git]
/
riscv
/
insns
/
lwu.h
1
require_xpr64
;
2
WRITE_RD
(
MMU
.
load_uint32
(
RS1
+
insn
.
i_imm
()));