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6c4ad769da911f5f2117708a965a89ae62b5e0fa
[riscv-isa-sim.git]
/
riscv
/
insns
/
lwu.h
1
require_xpr64
;
2
RD
=
MMU
.
load_uint32
(
RS1
+
insn
.
i_imm
());