6209e6f79c1f7717644b9381cda9bbeca8188b0f
[riscv-isa-sim.git] / riscv / insns / mfcr.h
1 reg_t val;
2
3 switch(insn.rtype.rs2)
4 {
5 case 0:
6 require_fp;
7 val = fsr;
8 break;
9
10 case 1:
11 val = 32; // synci_step
12 break;
13
14 default:
15 val = -1;
16 }
17
18 RD = gprlen == 64 ? val : sext32(val);