riscv/insns/mfpcr.h

   1 require_supervisor;
   2
   3 reg_t val;
   4
   5 switch(insn.rtype.rs2)
   6 {
   7   case 0:
   8     val = sr;
   9     break;
  10   case 1:
  11     val = epc;
  12     break;
  13   case 2:
  14     val = badvaddr;
  15     break;
  16   case 3:
  17     val = evec;
  18     break;
  19   case 4:
  20     val = count;
  21     break;
  22   case 5:
  23     val = compare;
  24     break;
  25   case 6:
  26     val = cause;
  27     break;
  28   case 7:
  29     val = mmu.get_ptbr();
  30     break;
  31
  32   case 10:
  33     val = id;
  34     break;
  35
  36   case 12:
  37     val = pcr_k0;
  38     break;
  39   case 13:
  40     val = pcr_k1;
  41     break;
  42
  43   case 17:
  44     val = sim.get_fromhost();
  45     break;
  46
  47   case 18:
  48     val = vecbanks;
  49     break;
  50
  51   default:
  52     val = -1;
  53 }
  54
  55 RD = sext_xprlen(val);