riscv/insns/mtc0.h

   1 require_supervisor;
   2
   3 switch(insn.rtype.rs)
   4 {
   5   case 0:
   6     set_sr(sext32(RT));
   7     break;
   8   case 1:
   9     epc = sext32(RT);
  10     break;
  11   case 3:
  12     ebase = sext32(RT & ~0xFFF);
  13     break;
  14
  15   case 16:
  16     sim->set_tohost(sext32(RT));
  17     break;
  18 }