d7b2b17eb2b1c9d6c689528ad0357da562f46bb9
[riscv-isa-sim.git] / riscv / insns / mtcr.h
1 switch(insn.rtype.rb)
2 {
3 case 0:
4 set_fsr(RA);
5 break;
6
7 case 29:
8 tid = RA;
9 break;
10 }