f63869d7b60aef8605ed86bbe9676460ac345178
[riscv-isa-sim.git] / riscv / insns / mulh.h
1 if(xpr64)
2 {
3 int64_t a = RS1;
4 int64_t b = RS2;
5 WRITE_RD((int128_t(a) * int128_t(b)) >> 64);
6 }
7 else
8 WRITE_RD(sext32((sext32(RS1) * sext32(RS2)) >> 32));