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3168ade2145f506b0ac7ad10d4ed07523e6ee6ec
[riscv-isa-sim.git]
/
riscv
/
insns
/
mulhsu.h
1
if
(
xpr64
)
2
WRITE_RD
(
mulhsu
(
RS1
,
RS2
));
3
else
4
WRITE_RD
(
sext32
((
sext32
(
RS1
) *
reg_t
((
uint32_t
)
RS2
)) >>
32
));