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90a17be019e35341a1c57ca1a3d361b23917955e
[riscv-isa-sim.git]
/
riscv
/
insns
/
mulhw.h
1
RC
=
sext32
((
sreg_t
(
RA
) *
sreg_t
(
RB
)) >>
32
);
2