0c06f476d0ce8e0bcc1f0f0ead636d2cd4cea1bf
[riscv-isa-sim.git] / riscv / insns / nmsub_d.h
1 require_fp;
2 FRC = f64_mulAdd(FRA, FRB, FRD ^ (uint64_t)INT64_MIN) ^ (uint64_t)INT64_MIN;
3 set_fp_exceptions;